HBLbits_Verilog Basic_Exams/2014 q3c

HBLbits_Verilog Basic_Exams/2014 q3c 

Given the state-assigned table shown below, implement the logic functions Y[0] and z.

module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);
    parameter A=3'b000,B=3'b001,C=3'b010,D=3'b011,E=3'b100; 
    reg[2:0] current_state, next_state;
    always@(*)begin
        case(current_state)
            A: next_state = x?B:A;
            B: next_state = x?E:B;
            C: next_state = x?B:C;
            D: next_state = x?C:B;
            E: next_state = x?E:D;
            default: next_state = A;
        endcase
    end
    assign Y0 = (x & y == 3'b000 || ~x & y == 3'b001 || x & y == 3'b010 || ~x & y == 3'b011 || ~x & y == 3'b100);
    assign z = (y == 3'b011 || y == 3'b100);
endmodule