HBLbits_Verilog Basic_Tb/tb1
Create a Verilog testbench that will produce the following waveform for outputs A and B:
`timescale 1ps / 1ps
module top_module ( output reg A, output reg B );//
// generate input patterns here
initial begin
A=0;B=0;
#10 A=1; //A=1,B=0;
#5 B=1; //A=1 B=1;
#5 A=0;
#20 B=0;
end
endmodule
// generate input patterns here
initial begin
A=0;B=0;
#10 A=1; //A=1,B=0;
#5 B=1; //A=1 B=1;
#5 A=0;
#20 B=0;
end
endmodule
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