HBLbits_Verilog Basic_Exams/2012 q2fsm

HBLbits_Verilog Basic_Exams/2012 q2fsm 

Consider the state diagram shown below.

Write complete Verilog code that represents this FSM. Use separate always blocks for the state table and the state flip-flops, as done in lectures. Describe the FSM output, which is called z, using either continuous assignment statement(s) or an always block (at your discretion). Assign any state codes that you wish to use.

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    input w,
    output z
);
    parameter A=3'b000,B=3'b001,C=3'b010,D=3'b011,E=3'b100,F=3'b101; 
    reg[2:0] current_state, next_state;
    
    always@(posedge clk)begin
        if(reset) current_state <= A;
        else current_state <= next_state;
    end
     always@(*)begin
        case(current_state)
            A: next_state = w?B:A;
            B: next_state = w?C:D;
            C: next_state = w?E:D;
            D: next_state = w?F:A;
            E: next_state = w?E:D;
            F: next_state = w?C:D;
            default: next_state = A;
        endcase
    end
  
    assign z = (current_state == E || current_state == F);   
    
endmodule