HBLbits_Verilog Basic_Tb/tb2

HBLbits_Verilog Basic_Tb/tb2 

The waveform below sets clk, in, and s:

Module q7 has the following declaration:

module q7 (
    input clk,
    input in,
    input [2:0] s,
    output out
);

Write a testbench that instantiates module q7 and generates these input signals exactly as shown in the waveform above.

`timescale 1ps / 1ps
module top_module();
    reg clk;
    reg in;
    reg [2:0] s;
    wire out;
    
    q7  dut(
        .clk(clk),
        .in(in),
        .s(s),
        .out(out)
    );
    
    initial begin
        clk=0;
        s = 3'b010;in=0;
        #10;
        s = 3'b110;
        #10;
        s = 3'b010;in=1;
        #10;
        s = 3'b111;in=0;
        #10;
        s = 3'b000;in=1; 
        #30;  in=0;       
    end

   
  always
begin
           #5 clk=~clk;
end     
endmodule