HBLbits_Verilog Basic_Bugs nand3

HBLbits_Verilog Basic_Bugs nand3 

This three-input NAND gate doesn't work. Fix the bug(s).

You must use the provided 5-input AND gate:

module andgate ( output out, input a, input b, input c, input d, input e );

Module Declaration

module top_module (input a, input b, input c, output out);

module top_module (input a, input b, input c, output out);//

    andgate inst1 ( a, b, c, out );

endmodule

module top_module (input a, input b, input c, output out);
    wire d,e,andout;
    assign d=1'b1;
    assign e=1'b1;
    assign out=~andout;
    andgate inst1 (andout,a,b,c,d,e);
endmodule
//module andgate ( output out, input a, input b, input c, input d, input e );