HBLbits_Verilog Basic_Exams/ece241 2014 q5b

HBLbits_Verilog Basic_Exams/ece241 2014 q5b

The following diagram is a Mealy machine implementation of the 2's complementer. Implement using one-hot encoding.

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    localparam A = 2'b01, B = 2'b10;
    reg [1:0] state, next_state;
    always@(*)begin
        case(state)
            A: next_state = x?B:A;
            B: next_state = x?B:B;
            default: next_state = A;
        endcase
    end
    
    always@(posedge clk or posedge areset) begin
        if(areset) state <= A;
        else state <= next_state;
    end
  
    reg z_mid;
    always@(*)begin
        case(state)
            A: z_mid = x?1:0;
            B: z_mid = x?0:1;
            default: z_mid = 0;
        endcase
    end
    assign z = z_mid;
endmodule