HBLbits_Verilog Basic_Fsm3s

 HBLbits_Verilog Basic_Fsm3s

See also: State transition logic for this FSM

The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous reset that resets the FSM to state A. (This is the same problem as Fsm3 but with a synchronous reset.)

State	Next state		Output
	in=0	in=1
A	A	B	0
B	C	B	0
C	A	D	0
D	C	B	1

module top_module(
    input clk,
    input in,
    input reset,
    output out); //
    parameter A=2'b00,B=2'b01,C=2'b10,D=2'b11;
    reg[1:0] present_state, next_state;
    always @(posedge clk) begin
        if (reset) begin  
            //  State flip-flops with synchronous reset
            present_state = A;
        end else begin
            case (present_state)
                //  State transition logic
                A: begin if(in) next_state = B; else next_state = A;end
                B: begin if(in) next_state = B; else next_state = C;end 
                C: begin if(in) next_state = D; else next_state = A;end
                D: begin if(in) next_state = B; else next_state = C;end 
                default:;                
            endcase
            // State flip-flops
            present_state = next_state;
        end
        case (present_state)
                // Output logic
    // Fill in state name declarations
                A: out <= 1'b0;
                B: out <= 1'b0;
                C: out <= 1'b0;
                D: out <= 1'b1;
                default:;
        endcase
    end
endmodule