HBLbits_Verilog Basic_Exams/2013 q2bfsm

HBLbits_Verilog Basic_Exams/2013 q2bfsm

 Consider a finite state machine that is used to control some type of motor. The FSM has inputs x and y, which come from the motor, and produces outputs f and g, which control the motor. There is also a clock input called clk and a reset input called resetn.

The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a beginning state, called state A. When the reset signal is de-asserted, then after the next clock edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to monitor the x input. When x has produced the values 1, 0, 1 in three successive clock cycles, then g should be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the FSM should set g = 0 permanently (until reset).

(The original exam question asked for a state diagram only. But here, implement the FSM.)

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
 parameter IDLE = 4'd0, S1 = 4'd1, S2 = 4'd2, S3 = 4'd3, S4 = 4'd4;
    parameter S5 = 4'd5, FOREVER_ONE = 4'd6, FOREVER_ZERO = 4'd7;
    parameter F_OUT = 4'd8;
    
    reg [3:0] current_state;
    reg [3:0] next_state;
    
    always@(posedge clk)begin
        if(resetn == 1'b0)begin
            current_state <= IDLE;
        end
        else begin
            current_state <= next_state;
        end
    end
    
    always@(*)begin
        case(current_state)
            IDLE:begin
                next_state = F_OUT;
            end
            F_OUT:begin
                next_state = S1;
            end
            S1:begin
                next_state = x ? S2 : S1;
            end
            S2:begin
                next_state = x ? S2 : S3;
            end
            S3:begin
                next_state = x ? S4 : S1;
            end  
            S4:begin
                next_state = y ? FOREVER_ONE : S5;
            end
            S5:begin
                next_state = y ? FOREVER_ONE : FOREVER_ZERO;
            end
            FOREVER_ONE:begin
                next_state = FOREVER_ONE;
            end
            FOREVER_ZERO:begin
                next_state = FOREVER_ZERO;
            end
            default:begin
                next_state = IDLE;
            end
        endcase
    end
    
    assign f = (current_state == F_OUT);
    assign g = (current_state == S4 || current_state == S5 || current_state == FOREVER_ONE);
 
endmodule