Verilog reg , Vectore , number , Array , Memory , parameter 使用

Verilog  reg , Vectore , number , Array , Memory , parameter 使用

//===========================
//4 bits Full Adder
 
 module parameter_ex ( In1,In2,Cin,Sum,Cout);

parameter Bits=4;
input  [Bits-1:0] In1,In2;
input  Cin;
output reg [Bits-1:0] Sum;
output reg Cout;

always @(In1,In2,Cin)
begin
{Cout,Sum}= {In1+In2+Cin};
end

endmodule

//===========================

`timescale 10ns/10ps

module TB;

 parameter Bits=4;
 // Inputs
 reg [Bits-1:0]In1;
 reg [Bits-1:0]In2;
 reg Cin;

 // Outputs
 wire [Bits-1:0]Sum;
 wire Cout;


 //Temporary looping variable
 reg [2:0] i = 3'd0;


 // Instantiate the Unit Under Test (UUT)

 parameter_ex UUT (

  .In1(In1),

  .In2(In2),

  .Cin(Cin),

  .Sum(Sum),

  .Cout(Cout)

  );

 initial begin

  // Initialize Inputs
  In1 = 4'd5;
  In2 = 4'd5;
  Cin = 1'b0;

  // Wait 100 ns for global reset to finish

  #30;


  // Add stimulus here

  for (i = 0; i < 8; i = i + 1'b1)begin

   {In1,In2,Cin} = {In1,In2,Cin} + 1'b1;

   #20;

  end

 end   

 initial begin
   #300  $stop;
 end


endmodule