//=============================
// Ch04 mux4_1.v
// 4 對 1 多工器 (閘層敘述)
module mux4_1 (A, B, C, D, S1, S0, Y);
input A,B,C,D,S1,S0; // 一位元輸入
output Y; // 一位元輸出
bufif1 (CD, D, S0);
bufif0 (CD, C, S0);
bufif1 (AB, B, S0);
bufif0 (AB, A, S0);
bufif1 ( Y, CD, S1);
bufif0 ( Y, AB, S1);
endmodule
`timescale 10ns/10ps
module T;
reg A = 1'b0;
reg B = 1'b1;
reg C = 1'b0;
reg D = 1'b1;
reg S1 = 1'b0;
reg S0 = 1'b0;
wire Y;
mux4_1 UUT (
.A(A),
.B(B),
.C(C),
.D(D),
.S1(S1),
.S0(S0),
.Y(Y));
initial
begin
#2400 // Final time: 2400 ns
$stop;
end
initial begin
// ------------- Current Time: 100ns
#100;
A = 1'b1; B = 1'b01; C = 1'b0; D = 1'b0;
S1 = 1'b0;S0 = 1'b0;
// -------------------------------------
// ------------- Current Time: 200ns
#100;
A = 1'b1; B = 1'b0; C = 1'b0; D = 1'b0;
S1 = 1'b0;S0 = 1'b1;
// -------------------------------------
// ------------- Current Time: 300ns
#100;
A = 1'b1; B = 1'b1; C = 1'b0; D = 1'b0;
S1 = 1'b0;S0 = 1'b1;
// -------------------------------------
// ------------- Current Time: 400ns
#100;
A = 1'b1; B = 1'b1; C = 1'b0; D = 1'b0;
S1 = 1'b1;S0 = 1'b0;
// -------------------------------------
// ------------- Current Time: 500ns
#100;
A = 1'b1; B = 1'b1; C = 1'b1; D = 1'b0;
S1 = 1'b1;S0 = 1'b0;
// -------------------------------------
// ------------- Current Time: 600ns
#100;
A = 1'b1; B = 1'b1; C = 1'b1; D = 1'b0;
S1 = 1'b1;S0 = 1'b1;
// -------------------------------------
// ------------- Current Time: 700ns
#100;
A = 1'b1; B = 1'b1; C = 1'b1; D = 1'b1;
S1 = 1'b1;S0 = 1'b1;
// -------------------------------------
// ------------- Current Time: 800ns
#100;
$stop;
end
endmodule
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