//===============================
// ex6-3.6 Full Substrator circuit
module EX10_14( A, B ,Bin ,Bout ,Diff);
input A,B,Bin ; // 1位元輸入
output reg Bout ,Diff ; // Output 1位元輸出
always@ ( A,B) begin
{Bout ,Diff}= A-B-Bin;
end
endmodule
//===============================
// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module Test_bench;
// Inputs
reg A,B,Bin;
// Outputs
wire Bout ,Diff ;
// Instantiate the Unit Under Test (UUT)
// ex6-3.5 Half Substrator circuit
EX10_14 UUT (
.A(A),
.B(B),
.Bin(Bin),
.Bout(Bout) ,
.Diff(Diff)
);
initial begin
$monitor( A, B ,Bin,Bout ,Diff);
//Apply inputs
A=1'b0; B=1'b0; Bin=1'b0;
#100;
{A,B,Bin}=3'b001;
#100;
{A,B,Bin}=3'b010;
#100;
{A,B,Bin}=3'b011;
#100;
{A,B,Bin}=3'b100;
#100;
{A,B,Bin}=3'b101;
#100;
{A,B,Bin}=3'b110;
#100;
{A,B,Bin}=3'b111;
#100;
end
initial begin
#800 $stop;
end
endmodule
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