Blocking And Nonblocking In Verilog

Blocking And Nonblocking In Verilog

源自於 http://www.asic-world.com/tidbits/blocking.html

//====================================
module blocking (clk,a,c);
input clk;
input a;
output c;

wire clk;
wire a;
reg c;
reg b;
 
always @ (posedge clk )
begin
 b = a;
 c = b;
end
 
endmodule


//====================================
`timescale 10ns/10ps

module Test_bench;
//blocking (clk,a,c)
reg clk=1'b0;
reg a;
wire c;

 blocking UUT (
        .clk(clk),
        .a(a),
        .c(c));
       
always #50 clk= ~clk;         
initial
begin
    #300 // Final time:  300 ns
    $stop;
end
 initial begin
      #65;
      a=1'b1;
     
      #65;
      a=1'b0;
     
      #65;
      a=1'b1;
       
      #65;
  $stop;
    end
endmodule

//====================================
module non_blocking (clk,a,c);
input clk;
input a;
output c;

wire clk;
wire a;
reg c;
reg b;
 
always @ (posedge clk )
begin
  b <= a;
  c <= b;
end
 
endmodule

//====================================
`timescale 10ns/10ps

module Test_bench;
//blocking (clk,a,c)
reg clk=1'b0;
reg a;
wire c;

 non_blocking UUT (
        .clk(clk),
        .a(a),
        .c(c));
       

     
always #50 clk= ~clk;         
initial
begin
    #300 // Final time:  300 ns
    $stop;
end
 initial begin
    $monitor ( clk,a,c);
      #65;
      a=1'b1;
     
      #65;
      a=1'b0;
     
      #65;
      a=1'b1;
       
      #65;
  $stop;
    end
endmodule

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