Verilog 4x1 MUX

Verilog 4x1 MUX

//4x1 mux
module mux_4x1(S0,S1,A,B,C,D,Y);
input S0,S1,A,B,C,D;
output Y;

wire w0,w1;
wire w00,w01,w10,w11;

not u1(w0,S0);
not u2(w1,s);

and u3(w00,w0,w1,A);
and u4(w01,S0,w1,B);
and u5(w10,w0,S1,C);
and u6(w11,S0,S1,D);

or  u7(Y,w00,w01,w10,w11);

endmodule

//=================================

// test bench

//=================================

`timescale 10ns/10ps

module Test_bech;

    reg A = 1'b0;

    reg B = 1'b0;

    reg C = 1'b0;

    reg D = 1'b0;

    

    reg S0 = 1'b0;

    reg S1 = 1'b0;

    

    wire Y;

//mux_4x1(S0,S1,A,B,C,D,Y);

    mux_4x1 UUT (

        .S0(S0),

        .S1(S1),

        .A(A),

        .B(B),

        .C(C),

        .D(D),

        .Y(Y));

    initial

    begin 

      #800; // Final time:  1000 ns

        $stop;

    end

    initial

    begin

        // -------------  Current Time:  100ns

        #100;

        S1=1'b0; S0=1'b0; A = 1'b1;B = 1'b0; C = 1'b0;D = 1'b0;

        // -------------------------------------

        // -------------  Current Time:  200ns

        #100;

        S1=1'b0; S0=1'b1; A = 1'b0;B = 1'b0; C = 1'b0;D = 1'b0;

        // -------------------------------------

        // -------------  Current Time:  300ns

        #100;

        S1=1'b0; S0=1'b1; A = 1'b0;B = 1'b1; C = 1'b0;D = 1'b0;

        // -------------------------------------

        // -------------  Current Time:  400ns

        #100;

        S1=1'b1; S0=1'b0; A = 1'b0;B = 1'b0; C = 1'b0;D = 1'b0;

        // -------------------------------------

        // -------------  Current Time:  500ns

        #100;

        S1=1'b1; S0=1'b0; A = 1'b0;B = 1'b0; C = 1'b1;D = 1'b0;

        // -------------------------------------

        // -------------  Current Time:  600ns

        #100;

        S1=1'b1; S0=1'b1; A = 1'b0;B = 1'b0; C = 1'b0;D = 1'b0;

        // -------------------------------------

        // -------------  Current Time:  700ns

        #100;

        S1=1'b1; S0=1'b1; A = 1'b0;B = 1'b0; C = 1'b0;D = 1'b1;

        // -------------------------------------

        // -------------  Current Time:  1000ns

    end

endmodule

//===================================

//Quartus 自動產生的程式

//===================================

module mux_gatelevel(

S0,

S1,

A,

B,

C,

D,

Y

);

input S0;

input S1;

input A;

input B;

input C;

input D;

output Y;

wire SYNTHESIZED_WIRE_8;

wire SYNTHESIZED_WIRE_9;

wire SYNTHESIZED_WIRE_4;

wire SYNTHESIZED_WIRE_5;

wire SYNTHESIZED_WIRE_6;

wire SYNTHESIZED_WIRE_7;

assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_8 & SYNTHESIZED_WIRE_9 & A;

assign SYNTHESIZED_WIRE_7 = S0 & SYNTHESIZED_WIRE_9 & B;

assign SYNTHESIZED_WIRE_5 = S1 & SYNTHESIZED_WIRE_8 & C;

assign SYNTHESIZED_WIRE_6 = S0 & S1 & D;

assign SYNTHESIZED_WIRE_8 =  ~S0;

assign SYNTHESIZED_WIRE_9 =  ~S1;

assign Y = SYNTHESIZED_WIRE_4 | SYNTHESIZED_WIRE_5 | SYNTHESIZED_WIRE_6 | SYNTHESIZED_WIRE_7;

endmodule

  剩下 Test bench 與 mux_4x1 才能 compilation