Verilog -DE2 http://letrthong.blogspot.tw/2012/03/verilog-de2.html
Digital Logic - Laboratory Exercises
Laboratory Exercise 1: Switches, Lights, and MultiplexersThe purpose of this exercise is to learn how to connect simple input and output devices to an FPGA chip and implement a circuit that uses these devices. We will use the switches SW170 on the DE2-series board as inputs to the circuit. We will use light emitting diodes (LEDs) and 7-segment displays as output devices.
Part I
The DE2-series board provides 18 toggle switches, called SW170, that can be used as inputs to a circuit, and 18 red lights, called LEDR170, that can be used to display output values. Figure 3 shows a simple Verilog module that uses these switches and shows their states on the LEDs. Since there are 18 switches and lights it is convenient to represent them as vectors in the Verilog code, as shown. We have used a single assignment statement for all 18 LEDR outputs, which is equivalent to the individual assignments
assign LEDR[17] = SW[17];
assign LEDR[16] = SW[16];
: : :
assign LEDR[0] = SW[0];
The DE2-series board has hardwired connections between its FPGA chip and the switches and lights. To use SW170 and LEDR170 it is necessary to include in your Quartus II project the correct pin assignments, which are given in the DE2-series User Manual. For example, the manual specifies that on the DE2 board, SW0 is connected to the FPGA pin N25 and LEDR0 is connected to pin AE23. On the DE2-70 board, SW0 is connected to the FPGA pin AA23 and LEDR0 is connected to pin AJ6. Moreover, on the DE2-115 board, SW0 is connected to the FPGA pin AB28 and LEDR0 is connected to pin G19. A good way to make the required pin assignments is to import into the Quartus II software the file called DE2_pin_assignments.qsf for the DE2 board, DE2_70_pin_assignments.qsf for the DE2-70 board, or DE2_115_pin_assignments.qsf for the DE2-115 board, which is provided on the DE2-Series System CD and in the University Program section of Altera’s web site. The procedure for making pin assignments is described in the tutorial Quartus II Introduction using Verilog Design, which is also available from Altera.
When importing the pin assignments file for the DE2-70 board, it is important to use Advanced Import Settings. To do so, click the Advanced... button on the Import Assignments screen as shown in Figure 1. Then,check Global assignments check box as shown in Figure 2 and press the OK button. Please note that omitting this step on a DE2-70 board may cause a compile time error.
It is important to realize that the pin assignments in the .qsf file are useful only if the pin names given in the file are exactly the same as the port names used in your Verilog module. The file uses the names SW[0] : : : SW[17] and LEDR[0] : : : LEDR[17] for the switches and lights, which is the reason we used these names in Figure 3.
// Simple module that connects the SW switches to the LEDR lights
module part1 (SW, LEDR);
input [17:0] SW; // toggle switches
output [17:0] LEDR; // red LEDs
assign LEDR = SW;
endmodule
Figure 3. Verilog code that uses the DE2-series board switches and lights.
Perform the following steps to implement a circuit corresponding to the code in Figure 3 on the DE2-series board.
1. Create a new Quartus II project for your circuit. If using the Altera DE2 board, select Cyclone II EP2C35F672C6 as the target chip, which is its FPGA chip. Select Cyclone II EP2C70F896C6 if using the DE2-70 board. Or, select Cyclone IV EP4CE115F29C7 if using the DE2-115 board.
2. Create a Verilog module for the code in Figure 3 and include it in your project.
3. Include in your project the required pin assignments for the DE2-series board, as discussed above. Compilethe project.
4. Download the compiled circuit into the FPGA chip. Test the functionality of the circuit by toggling theswitches and observing the LEDs.
step1 :Create project
a .File / New project Wizard
b . fill information / Next
c. select Cyclone II EP2C35F672C6 / Finish
A . File /New / Verilog HDL file/OK
//---------------------------------------
module part1 (SW, LEDR);
input [17:0] SW; // toggle switches
output [17:0] LEDR; // red LEDs
assign LEDR = SW;
endmodule
//-----------------------------------------
C / Assignments / Import assignments file DE2_70_pin_assignments.qsf
D / Processing / start_compilation
E/ Tools / programmer/ start
Part II
Figure 4a shows a sum-of-products circuit that implements a 2-to-1 multiplexer with a select input s. If s = 0 the multiplexer’s output m is equal to the input x, and if s = 1 the output is equal to y. Part b of the figure gives a truth table for this multiplexer, and part c shows its circuit symbol.
You are to write a Verilog module that includes eight assignment statements like the one shown above to
describe the circuit given in Figure 5a. This circuit has two eight-bit inputs, X and Y , and produces the eight-bit output M. If s = 0 then M = X, while if s = 1 then M = Y . We refer to this circuit as an eight-bit wide 2-to-1 multiplexer. It has the circuit symbol shown in Figure 5b, in which X, Y , and M are depicted as eight-bit wires.
Perform the steps shown below.
2. Include your Verilog file for the eight-bit wide 2-to-1 multiplexer in your project. Use switch SW17 on the DE2-series board as the s input, switches SW70 as the X input and SW158 as the Y input. Connect the
SW switches to the red lights LEDR and connect the output M to the green lights LEDG70.
3. Include in your project the required pin assignments for the DE2-series board. As discussed in Part I,
these assignments ensure that the input ports of your Verilog code will use the pins on the FPGA that are
connected to the SW switches, and the output ports of your Verilog code will use the FPGA pins connected
to the LEDR and LEDG lights.
4. Compile the project.
5. Download the compiled circuit into the FPGA chip. Test the functionality of the eight-bit wide 2-to-1
multiplexer by toggling the switches and observing the LEDs.
code verilog part2.v
//----------------------------------------
module part2(SW,LEDR,LEDG);
input [17:0]SW;
output [17:0]LEDR;
output [7:0]LEDG;
assign LEDR = SW;
assign LEDG[7:0] = (SW[17] == 0 )?SW[7:0]:SW[15:8] ;
// x = SW[7:0]
// y = Sw[15:0];
//m = LEDG[7:0];
//m = (~s & x) | (s & y)
endmodule
//----------------------------------------
Part III
In Figure 4 we showed a 2-to-1 multiplexer that selects between the two inputs x and y. For this part consider a circuit in which the output m has to be selected from five inputs u, v, w, x, and y. Part a of Figure 6 shows how we can build the required 5-to-1 multiplexer by using four 2-to-1 multiplexers. The circuit uses a 3-bit select input s2s1s0 and implements the truth table shown in Figure 6b. A circuit symbol for this multiplexer is given in part c of the figure.
Recall from Figure 5 that an eight-bit wide 2-to-1 multiplexer can be built by using eight instances of a 2-to-1 multiplexer. Figure 7 applies this concept to define a three-bit wide 5-to-1 multiplexer. It contains three instances of the circuit in Figure 6a.
Perform the following steps to implement the three-bit wide 5-to-1 multiplexer.
1. Create a new Quartus II project for your circuit.
2. Create a Verilog module for the three-bit wide 5-to-1 multiplexer. Connect its select inputs to switches
SW1715, and use the remaining 15 switches SW140 to provide the five 3-bit inputs U to Y . Connect the
SW switches to the red lights LEDR and connect the output M to the green lights LEDG20.
3. Include in your project the required pin assignments for the DE2-series board. Compile the project.
4. Download the compiled circuit into the FPGA chip. Test the functionality of the three-bit wide 5-to-1
multiplexer by toggling the switches and observing the LEDs. Ensure that each of the inputs U to Y can be
properly selected as the output M.
code verilog part3.v
//---------------------------------------------------------------
module part3(SW,LEDR,LEDG);
input [17:0]SW;
output [17:0]LEDR;
output [2:0]LEDG;
assign LEDR = SW;
assign LEDG[2:0] = (SW[17:15] == 3'b000 )? SW[2:0]:
(SW[17:15] == 3'b001 )? SW[5:3]:
(SW[17:15] == 3'b010 )? SW[8:6]:
(SW[17:15] == 3'b011 )? SW[11:9]:SW[14:12] ;
endmodule
//----------------------------------------------------------------
//----------------------------------------------------------------
Part IV
Figure 8 shows a 7-segment decoder module that has the three-bit input c2c1c0. This decoder produces seven outputs that are used to display a character on a 7-segment display. Table 1 lists the characters that should be displayed for each valuation of c2c1c0. To keep the design simple, only four characters are included in the table (plus the ‘blank’ character, which is selected for codes 100 111).
The seven segments in the display are identified by the indices 0 to 6 shown in the figure. Each segment is
illuminated by driving it to the logic value 0. You are to write a Verilog module that implements logic functions that represent circuits needed to activate each of the seven segments. Use only simple Verilog assign statements
in your code to specify each logic function using a Boolean expression.
Perform the following steps:
1. Create a new Quartus II project for your circuit.
2. Create a Verilog module for the 7-segment decoder. Connect the c2c1c0 inputs to switches SW20, and
connect the outputs of the decoder to the HEX0 display on the DE2-series board. The segments in this
display are called HEX00, HEX01, : : :, HEX06, corresponding to Figure 8. You should declare the 7-bit port output [0:6] HEX0;
in your Verilog code so that the names of these outputs match the corresponding names in the DE2-series
User Manual and the pin assignments file.
3. After making the required DE2-series board pin assignments, compile the project.
4. Download the compiled circuit into the FPGA chip. Test the functionality of the circuit by toggling the
SW20 switches and observing the 7-segment display.
code verilog part4.v
//---------------------------------------
module part4(SW,HEX0);
input [2:0]SW;
output [6:0]HEX0;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off
// ---a----
// | |
// f b
// | |
// ---g----
// | |
// e c
// | |
// ---d----
assign HEX0= (SW[2:0] == 3'b000 )? 7'b000_1001: // H
(SW[2:0] == 3'b001 )?7'b000_0110: //E
(SW[2:0] == 3'b010 )?7'b100_0111: //L
(SW[2:0] == 3'b011 )?7'b100_0000:7'b111_1111 ; // 0
endmodule
//-------------------------------------------------------------
Part V
Consider the circuit shown in Figure 9. It uses a three-bit wide 5-to-1 multiplexer to enable the selection of five characters that are displayed on a 7-segment display. Using the 7-segment decoder from Part IV this circuit can display any of the characters H, E, L, O, and ‘blank’. The character codes are set according to Table 1 by using the switches SW140, and a specific character is selected for display by setting the switches SW1715. An outline of the Verilog code that represents this circuit is provided in Figure 10. Note that we have used the circuits from Parts III and IV as subcircuits in this code. You are to extend the code in Figure 10 so that it uses five 7-segment displays rather than just one. You will need to use five instances of each of the subcircuits. The purpose of your circuit is to display any word on the five displays that is composed of the characters in Table 1, and be able to rotate this word in a circular fashion across the displays when the switches SW1715 are toggled. As an example, if the displayed word is HELLO, then your circuit should produce the output patterns illustrated in Table 2.
module part5 (SW, HEX0);
input [17:0] SW; // toggle switches
output [0:6] HEX0; // 7-seg displays
wire [2:0] M;
mux_3bit_5to1 M0 (SW[17:15], SW[14:12], SW[11:9], SW[8:6], SW[5:3], SW[2:0], M);
char_7seg H0 (M, HEX0);
endmodule
// implements a 3-bit wide 5-to-1 multiplexer
module mux_3bit_5to1 (S, U, V, W, X, Y, M);
input [2:0] S, U, V, W, X, Y;
output [2:0] M;
: : : code not shown
endmodule
// implements a 7-segment decoder for H, E, L, O, and ‘blank’
module char_7seg (C, Display);
input [2:0] C; // input code
output [0:6] Display; // output 7-seg code
: : : code not shown
endmodule
Perform the following steps.
1. Create a new Quartus II project for your circuit.
2. Include your Verilog module in the Quartus II project. Connect the switches SW1715 to the select inputs of each of the five instances of the three-bit wide 5-to-1 multiplexers. Also connect SW140 to each instance
of the multiplexers as required to produce the patterns of characters shown in Table 2. Connect the outputs
of the five multiplexers to the 7-segment displays HEX4, HEX3, HEX2, HEX1, and HEX0.
3. Include the required pin assignments for the DE2-series board for all switches, LEDs, and 7-segment displays. Compile the project.
4. Download the compiled circuit into the FPGA chip. Test the functionality of the circuit by setting the proper character codes on the switches SW140 and then toggling SW1715 to observe the rotation of the characters.
code verilog part5.v
//--------------------------------------------------------------
module part1(SW, HEX4,HEX3,HEX2,HEX1,HEX0);
input [17:0] SW; // toggle switches
output [6:0]HEX4,HEX3,HEX2,HEX1,HEX0; // 7-seg displays
wire [2:0] M4,M3,M2,M1,M0;
//SW[14:12] H
// SW[11:9] E
// SW[8:6] L
//SW[5:3] L
// SW[2:0] 0 // H E L L O
mux_3bit_5to1 m4(SW[17:15], SW[14:12], SW[11:9], SW[8:6], SW[5:3], SW[2:0], M4);
mux_3bit_5to1 m3(SW[17:15], SW[11:9], SW[8:6], SW[5:3], SW[2:0], SW[14:12], M3);
mux_3bit_5to1 m2(SW[17:15], SW[8:6], SW[5:3] , SW[2:0], SW[14:12], SW[11:9], M2);
mux_3bit_5to1 m1(SW[17:15], SW[5:3], SW[2:0], SW[14:12], SW[11:9], SW[8:6],M1);
mux_3bit_5to1 m0(SW[17:15], SW[2:0], SW[14:12], SW[11:9], SW[8:6], SW[5:3], M0);
char_7seg h4(M4, HEX4);
char_7seg h3(M3, HEX3);
char_7seg h2(M2, HEX2);
char_7seg h1(M1, HEX1);
char_7seg h0(M0, HEX0);
endmodule
//-------------------------------------------------------
// implements a 3-bit wide 5-to-1 multiplexer
module mux_3bit_5to1(S, U, V, W, X, Y, M);
input [2:0] S, U, V, W, X, Y;
output [2:0] M;
assign M = (S== 3'b000 )? U:
(S == 3'b001 )? V:
(S == 3'b010 )? W:
(S == 3'b011 )? X:Y ;
endmodule
//-----------------------------------------------------------
// implements a 7-segment decoder for H, E, L, O, and ‘blank’
module char_7seg(sw,hex);
input [2:0]sw;
output [6:0]hex;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off
// ---a----
// | |
// f b
// | |
// ---g----
// | |
// e c
// | |
// ---d----
assign hex= (sw[2:0] == 3'b000 )? 7'b000_1001: // H
(sw[2:0] == 3'b001 )?7'b000_0110: //E
(sw[2:0] == 3'b010 )?7'b100_0111: //L
(sw[2:0] == 3'b011 )?7'b100_0000:7'b111_1111 ; // 0
endmodule
//----------------------------------------------------------
Part VI
Extend your design from Part V so that is uses all eight 7-segment displays on the DE2 board. Your circuit should be able to display words with five (or fewer) characters on the eight displays, and rotate the displayed word when the switches SW1715 are toggled. If the displayed word is HELLO, then your circuit should produce the patterns shown in Table 3.
Perform the following steps:
1. Create a new Quartus II project for your circuit and select the appropriate target chip.
2. Include your Verilog module in the Quartus II project. Connect the switches SW1715 to the select inputs of each instance of the multiplexers in your circuit. Also connect SW140 to each instance of the multiplexers
as required to produce the patterns of characters shown in Table 3. (Hint: for some inputs of the multiplexers
you will want to select the ‘blank’ character.) Connect the outputs of your multiplexers to the 7-segment
displays HEX7, : : :, HEX0.
3. Include the required pin assignments for the DE2-series board for all switches, LEDs, and 7-segment displays. Compile the project.
4. Download the compiled circuit into the FPGA chip. Test the functionality of the circuit by setting the proper character codes on the switches SW140 and then toggling SW1715 to observe the rotation of the characters.
code verilog part6.v
//-----------------------------------------------------------------------
module part1(SW, HEX7,HEX6,HEX5 ,HEX4,HEX3,HEX2,HEX1,HEX0);
input [17:0] SW; // toggle switches
output [6:0]HEX7,HEX6,HEX5 ,HEX4,HEX3,HEX2,HEX1,HEX0; // 7-seg displays
wire [2:0] M7,M6,M5,M4,M3,M2,M1,M0;
wire [2:0]sw2,sw1,sw0 ;
assign sw2 =3'b111;
assign sw1 =3'b111;
assign sw0 =3'b111;
//SW[14:12] H
// SW[11:9] E
// SW[8:6] L
//SW[5:3] L
// SW[2:0] 0 // H E L L O
mux_3bit_8to1 m7(SW[17:15],sw2 ,sw1 , sw0 , SW[14:12], SW[11:9], SW[8:6], SW[5:3], SW[2:0], M7);
mux_3bit_8to1 m6(SW[17:15],sw1 , sw0 , SW[14:12], SW[11:9], SW[8:6], SW[5:3], SW[2:0], sw2 ,M6);
mux_3bit_8to1 m5(SW[17:15],sw0 , SW[14:12], SW[11:9], SW[8:6], SW[5:3], SW[2:0], sw2 ,sw1 , M5);
mux_3bit_8to1 m4(SW[17:15],SW[14:12], SW[11:9], SW[8:6], SW[5:3], SW[2:0], sw2 ,sw1 ,sw0, M4);
mux_3bit_8to1 m3(SW[17:15],SW[11:9], SW[8:6], SW[5:3], SW[2:0], sw2 ,sw1 ,sw0,SW[14:12], M3);
mux_3bit_8to1 m2(SW[17:15],SW[8:6], SW[5:3], SW[2:0], sw2 ,sw1 ,sw0,SW[14:12],SW[11:9], M2);
mux_3bit_8to1 m1(SW[17:15], SW[5:3], SW[2:0], sw2 ,sw1 ,sw0,SW[14:12],SW[11:9],SW[8:6], M1);
mux_3bit_8to1 m0(SW[17:15],SW[2:0], sw2 ,sw1 ,sw0,SW[14:12],SW[11:9],SW[8:6], SW[5:3], M0);
char_7seg h7(M7, HEX7);
char_7seg h6(M6, HEX6);
char_7seg h5(M5, HEX5);
char_7seg h4(M4, HEX4);
char_7seg h3(M3, HEX3);
char_7seg h2(M2, HEX2);
char_7seg h1(M1, HEX1);
char_7seg h0(M0, HEX0);
endmodule
/----------------------------------------------------------
// implements a 3-bit wide 5-to-1 multiplexer
module mux_3bit_8to1(S, U, V, W, X, Y, J,K,L,M);
input [2:0] S, U, V, W, X, Y,J,K,L;
output [2:0] M;
assign M = (S== 3'b000 )? U:
(S == 3'b001 )? V:
(S == 3'b010 )? W:
(S == 3'b011 )? X:
(S == 3'b100 )? Y:
(S == 3'b101 )? J:
(S == 3'b110 )? K:L ;
endmodule
// implements a 7-segment decoder for H, E, L, O, and ‘blank’
//---------------------------------------------------------
module char_7seg(sw,hex);
input [2:0]sw;
output [6:0]hex;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off
// ---a----
// | |
// f b
// | |
// ---g----
// | |
// e c
// | |
// ---d----
assign hex= (sw[2:0] == 3'b000 )? 7'b000_1001: // H
(sw[2:0] == 3'b001 )?7'b000_0110: //E
(sw[2:0] == 3'b010 )?7'b100_0111: //L
(sw[2:0] == 3'b011 )?7'b100_0000:7'b111_1111 ; // 0
endmodule
TP.Ho Chi Minh 31/03/2012
//-------------------------------------------------------------------------------------------------------------------------------
Laboratory Exercise 2 :Numbers and Displays
This is an exercise in designing combinational circuits that can perform binary-to-decimal number conversion
and binary-coded-decimal (BCD) addition.
Part I
We wish to display on the 7-segment displays HEX3 to HEX0 the values set by the switches SW150. Let the values denoted by SW1512, SW118, SW74 and SW30 be displayed on HEX3, HEX2, HEX1 and HEX0, respectively. Your circuit should be able to display the digits from 0 to 9, and should treat the valuations 1010 to 1111 as don’t-cares.
1. Create a new project which will be used to implement the desired circuit on the Altera DE2-series board.
The intent of this exercise is to manually derive the logic functions needed for the 7-segment displays. You
should use only simple Verilog assign statements in your code and specify each logic function as a Boolean
expression.
2. Write a Verilog file that provides the necessary functionality. Include this file in your project and assign
the pins on the FPGA to connect to the switches and 7-segment displays, as indicated in the User Manual
for the DE2-series board. The procedure for making pin assignments is described in the tutorial Quartus II
Introduction using Verilog Design, which is available on the DE2-Series System CD and in the University
Program section of Altera’s web site.
3. Compile the project and download the compiled circuit into the FPGA chip.
4. Test the functionality of your design by toggling the switches and observing the displays.
code verilog part1.v
//--------------------------------------------------------
module part1(SW, HEX3,HEX2,HEX1,HEX0);
input [15:0] SW; // toggle switches
output [6:0]HEX3,HEX2,HEX1,HEX0; // 7-seg displays
char_7seg h3(SW[15:12],HEX3);
char_7seg h2(SW[11:8],HEX2);
char_7seg h1(SW[7:4],HEX1);
char_7seg h0(SW[3:0],HEX0);
endmodule
//------------------------------------------------------
module char_7seg(sw,hex);
input [3:0]sw;
output [6:0]hex;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off
// ---a----
// | |
// f b
// | |
// ---g----
// | |
// e c
// | |
// ---d----
assign hex= (sw[3:0] == 4'b0000 )? 7'b000_0000: // 0
(sw[3:0] == 4'b0001 )? 7'b111_1001: //1
(sw[3:0] == 4'b0010 )? 7'b010_0100: //2
(sw[3:0] == 4'b0011 )? 7'b011_0000: // 3
(sw[3:0] == 4'b0100 )? 7'b001_1001: // 4
(sw[3:0] == 4'b0101 )? 7'b001_0010: // 5
(sw[3:0] == 4'b0110 )? 7'b000_0010: // 6
(sw[3:0] == 4'b0111 )? 7'b111_1000: // 7
(sw[3:0] == 4'b1000 )? 7'b000_0000: // 8
(sw[3:0] == 4'b1001 )? 7'b001_0000: 7'b111_1111; // 9 - black
endmodule
//----------------------------------------------------------------
Part II
You are to design a circuit that converts a four-bit binary number V = v3v2v1v0 into its two-digit decimal equivalent D = d1d0. Table 1 shows the required output values. A partial design of this circuit is given in Figure 1. Itincludes a comparator that checks when the value of V is greater than 9, and uses the output of this comparator in the control of the 7-segment displays. You are to complete the design of this circuit by creating a Verilog module which includes the comparator, multiplexers, and circuit A (do not include circuit B or the 7-segment decoder at this point). Your Verilog module should have the four-bit input V , the four-bit output M and the output z. The intent of this exercise is to use simple Verilog assign statements to specify the required logic functions using Boolean expressions. Your Verilog code should not include any if-else, case, or similar statements.
Perform the following steps:
1. Make a Quartus II project for your Verilog module.
2. Compile the circuit and use functional simulation to verify the correct operation of your comparator, multiplexers, and circuit A.
3. Augment your Verilog code to include circuit B in Figure 1 as well as the 7-segment decoder. Change the
inputs and outputs of your code to use switches SW30 on the DE2-series board to represent the binary
number V , and the displays HEX1 and HEX0 to show the values of decimal digits d1 and d0. Make sure to
include in your project the required pin assignments for the DE2-series board.
4. Recompile the project, and then download the circuit into the FPGA chip.
5. Test your circuit by trying all possible values of V and observing the output displays.
* 1 - bit comparator
a b q
0 0 1
0 1 0
1 0 0
1 1 1
q= a'b'+ ab;
code verilog
//-------------------------------------
module eql (
input wire a,b,
output wire q ) ;
wire p0, pl;
assign q = p0 |p1;
assign p0 = ~a & ~b;
assign pl = a & b;
endmodule
//-----------------------------------
* 2-bits comparator
a[1:0] b [1:0] q
00 00 1
00 01 0
00 10 0
00 11 0
01 00 0
01 01 1
01 10 0
01 11 0
10 00 0
10 01 0
10 10 1
10 11 0
11 00 0
11 01 0
11 10 0
11 11 1
q = a[1] 'a[0]'b[1]'b[0]' +a[1]' a[0] b[1]'b[0] +a[1] a[0]'b[1]b[0] '+a[1] a[0]b[1]b[0] ;
code verilog
//--------------------------------------------------
module eq2 (
input wire[1:0] a,b,
output wire q ) ;
wire q3, q2,q1,q0;
assign q = q3|q2|q1|q0;
assign q3 = ( ~a[1] &~ a[0] ) & (~b[1] &~b[0]);
assign q2 = ( ~a[1] & a[0] ) & (~b[1] &b[0]);
assign q1 = ( a[1] &~ a[0] ) & (b[1] &~b[0]);
assign q0 = ( a[1] & a[0] ) & (b[1] &b[0]);
endmodule
//------------------------------------------------
module eq2 (
input wire[1:0] a,b,
output wire q ) ;
wire q1, q0;
eql bit0(a[0], b[0], q0);
eql bit1( a[1], b[1], q1 );
assign q = q0&q1;
endmodule
//-------------------------------------------------
4-bits binary to decimal conversion
//------------------------------------------
module part2(SW,HEX1,HEX0);
input [3:0]SW;
output [6:0]HEX1,HEX0;
wire z ;
wire [3:0]y , m;
wire [2:0]b;
assign y = {1'b0,b};
//-------------------------
comparator compar1(SW[3],SW[2],SW[1],SW[0],z);
circuitA circuita(SW[2:0],b[2:0]);
multi multi1(z,SW[3:0],y,m);
circuitB hex1(z,HEX1);
char_7seg hex0(m , HEX0 );
//-------------------------
endmodule
//------------------------------------------
module comparator(a,b,c,d,q);
input a,b,c,d;
output q ;
wire q5,q4,q3,q2,q1,q0;
assign q = q5|q4|q3|q2|q1|q0;
assign q5 = a&~b&c&~d; //10
assign q4 = a&~b&c&d; //11
assign q3 = a&b&~c&~d; //12
assign q2 = a&b&~c&d; //13
assign q1 = a&b&c&~d; //14
assign q0 = a&b&c&d; //15
endmodule
//-----------------------------------------
module circuitA(a,b);
input [2:0]a;
output [2:0]b;
assign b[2:0] = (a[2:0] == 3'b010) ?3'b000 :
(a[2:0] == 3'b011) ?3'b001 :
(a[2:0] == 3'b100) ?3'b010 :
(a[2:0] == 3'b101) ?3'b011 :
(a[2:0] == 3'b110) ?3'b100 :
(a[2:0] == 3'b111) ?3'b101 :3'b111;
endmodule
//--------------------------------------
module circuitB(a,hex);
input [0:0]a;
output [6:0]hex;
assign hex[6:0] = (a[0] == 1'b1)? 7'b111_1001 : 7'b100_0000; // 1 - 0
endmodule
//-----------------------------------------
module multi(s,x,y,m);
input s;
input [3:0]x,y;
output [3:0]m;
assign m[3] = (~s&x[3] ) | (s&y[3]);
assign m[2] = (~s&x[2] ) | (s&y[2]);
assign m[1] = (~s&x[1] ) | (s&y[1]);
assign m[0] = (~s&x[0] ) | (s&y[0]);
endmodule
//------------------------------------------
module char_7seg(sw,hex);
input [3:0]sw;
output [6:0]hex;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off
// ---a----
// | |
// f b
// | |
// ---g----
// | |
// e c
// | |
// ---d----
assign hex= (sw[3:0] == 4'b0000 )? 7'b000_0000: // 0
(sw[3:0] == 4'b0001 )? 7'b111_1001: //1
(sw[3:0] == 4'b0010 )? 7'b010_0100: //2
(sw[3:0] == 4'b0011 )? 7'b011_0000: // 3
(sw[3:0] == 4'b0100 )? 7'b001_1001: // 4
(sw[3:0] == 4'b0101 )? 7'b001_0010: // 5
(sw[3:0] == 4'b0110 )? 7'b000_0010: // 6
(sw[3:0] == 4'b0111 )? 7'b111_1000: // 7
(sw[3:0] == 4'b1000 )? 7'b000_0000: // 8
(sw[3:0] == 4'b1001 )? 7'b001_0000: 7'b111_1111; // 9 - black
endmodule
//----------------------------------------------------------------
Part III
Figure 2a shows a circuit for a full adder, which has the inputs a, b, and ci , and produces the outputs s and co. Parts b and c of the figure show a circuit symbol and truth table for the full adder, which produces the two-bit binary sum cos = a + b + ci . Figure 2d shows how four instances of this full adder module can be used to design a circuit that adds two four-bit numbers. This type of circuit is usually called a ripple-carry adder, because of the way that the carry signals are passed from one full adder to the next. Write Verilog code that implements this circuit, as described below.
1. Create a new Quartus II project for the adder circuit. Write a Verilog module for the full adder subcircuit
and write a top-level Verilog module that instantiates four instances of this full adder.
2. Use switches SW74 and SW30 to represent the inputs A and B, respectively. Use SW8 for the carry-in
cin of the adder. Connect the SW switches to their corresponding red lights LEDR, and connect the outputs
of the adder, cout and S, to the green lights LEDG.
3. Include the necessary pin assignments for the DE2-series board, compile the circuit, and download it into
the FPGA chip.
4. Test your circuit by trying different values for numbers A, B, and cin.
Extend your design from Part V so that is uses all eight 7-segment displays on the DE2 board. Your circuit should be able to display words with five (or fewer) characters on the eight displays, and rotate the displayed word when the switches SW1715 are toggled. If the displayed word is HELLO, then your circuit should produce the patterns shown in Table 3.
Perform the following steps:
1. Create a new Quartus II project for your circuit and select the appropriate target chip.
2. Include your Verilog module in the Quartus II project. Connect the switches SW1715 to the select inputs of each instance of the multiplexers in your circuit. Also connect SW140 to each instance of the multiplexers
as required to produce the patterns of characters shown in Table 3. (Hint: for some inputs of the multiplexers
you will want to select the ‘blank’ character.) Connect the outputs of your multiplexers to the 7-segment
displays HEX7, : : :, HEX0.
3. Include the required pin assignments for the DE2-series board for all switches, LEDs, and 7-segment displays. Compile the project.
4. Download the compiled circuit into the FPGA chip. Test the functionality of the circuit by setting the proper character codes on the switches SW140 and then toggling SW1715 to observe the rotation of the characters.
code verilog part6.v
//-----------------------------------------------------------------------
module part1(SW, HEX7,HEX6,HEX5 ,HEX4,HEX3,HEX2,HEX1,HEX0);
input [17:0] SW; // toggle switches
output [6:0]HEX7,HEX6,HEX5 ,HEX4,HEX3,HEX2,HEX1,HEX0; // 7-seg displays
wire [2:0] M7,M6,M5,M4,M3,M2,M1,M0;
wire [2:0]sw2,sw1,sw0 ;
assign sw2 =3'b111;
assign sw1 =3'b111;
assign sw0 =3'b111;
//SW[14:12] H
// SW[11:9] E
// SW[8:6] L
//SW[5:3] L
// SW[2:0] 0 // H E L L O
mux_3bit_8to1 m7(SW[17:15],sw2 ,sw1 , sw0 , SW[14:12], SW[11:9], SW[8:6], SW[5:3], SW[2:0], M7);
mux_3bit_8to1 m6(SW[17:15],sw1 , sw0 , SW[14:12], SW[11:9], SW[8:6], SW[5:3], SW[2:0], sw2 ,M6);
mux_3bit_8to1 m5(SW[17:15],sw0 , SW[14:12], SW[11:9], SW[8:6], SW[5:3], SW[2:0], sw2 ,sw1 , M5);
mux_3bit_8to1 m4(SW[17:15],SW[14:12], SW[11:9], SW[8:6], SW[5:3], SW[2:0], sw2 ,sw1 ,sw0, M4);
mux_3bit_8to1 m3(SW[17:15],SW[11:9], SW[8:6], SW[5:3], SW[2:0], sw2 ,sw1 ,sw0,SW[14:12], M3);
mux_3bit_8to1 m2(SW[17:15],SW[8:6], SW[5:3], SW[2:0], sw2 ,sw1 ,sw0,SW[14:12],SW[11:9], M2);
mux_3bit_8to1 m1(SW[17:15], SW[5:3], SW[2:0], sw2 ,sw1 ,sw0,SW[14:12],SW[11:9],SW[8:6], M1);
mux_3bit_8to1 m0(SW[17:15],SW[2:0], sw2 ,sw1 ,sw0,SW[14:12],SW[11:9],SW[8:6], SW[5:3], M0);
char_7seg h7(M7, HEX7);
char_7seg h6(M6, HEX6);
char_7seg h5(M5, HEX5);
char_7seg h4(M4, HEX4);
char_7seg h3(M3, HEX3);
char_7seg h2(M2, HEX2);
char_7seg h1(M1, HEX1);
char_7seg h0(M0, HEX0);
endmodule
/----------------------------------------------------------
// implements a 3-bit wide 5-to-1 multiplexer
module mux_3bit_8to1(S, U, V, W, X, Y, J,K,L,M);
input [2:0] S, U, V, W, X, Y,J,K,L;
output [2:0] M;
assign M = (S== 3'b000 )? U:
(S == 3'b001 )? V:
(S == 3'b010 )? W:
(S == 3'b011 )? X:
(S == 3'b100 )? Y:
(S == 3'b101 )? J:
(S == 3'b110 )? K:L ;
endmodule
// implements a 7-segment decoder for H, E, L, O, and ‘blank’
//---------------------------------------------------------
module char_7seg(sw,hex);
input [2:0]sw;
output [6:0]hex;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off
// ---a----
// | |
// f b
// | |
// ---g----
// | |
// e c
// | |
// ---d----
assign hex= (sw[2:0] == 3'b000 )? 7'b000_1001: // H
(sw[2:0] == 3'b001 )?7'b000_0110: //E
(sw[2:0] == 3'b010 )?7'b100_0111: //L
(sw[2:0] == 3'b011 )?7'b100_0000:7'b111_1111 ; // 0
endmodule
//-------------------------------------------------------------
TP.Ho Chi Minh 31/03/2012
//-------------------------------------------------------------------------------------------------------------------------------
Laboratory Exercise 2 :Numbers and Displays
This is an exercise in designing combinational circuits that can perform binary-to-decimal number conversion
and binary-coded-decimal (BCD) addition.
Part I
We wish to display on the 7-segment displays HEX3 to HEX0 the values set by the switches SW150. Let the values denoted by SW1512, SW118, SW74 and SW30 be displayed on HEX3, HEX2, HEX1 and HEX0, respectively. Your circuit should be able to display the digits from 0 to 9, and should treat the valuations 1010 to 1111 as don’t-cares.
1. Create a new project which will be used to implement the desired circuit on the Altera DE2-series board.
The intent of this exercise is to manually derive the logic functions needed for the 7-segment displays. You
should use only simple Verilog assign statements in your code and specify each logic function as a Boolean
expression.
2. Write a Verilog file that provides the necessary functionality. Include this file in your project and assign
the pins on the FPGA to connect to the switches and 7-segment displays, as indicated in the User Manual
for the DE2-series board. The procedure for making pin assignments is described in the tutorial Quartus II
Introduction using Verilog Design, which is available on the DE2-Series System CD and in the University
Program section of Altera’s web site.
3. Compile the project and download the compiled circuit into the FPGA chip.
4. Test the functionality of your design by toggling the switches and observing the displays.
code verilog part1.v
//--------------------------------------------------------
module part1(SW, HEX3,HEX2,HEX1,HEX0);
input [15:0] SW; // toggle switches
output [6:0]HEX3,HEX2,HEX1,HEX0; // 7-seg displays
char_7seg h3(SW[15:12],HEX3);
char_7seg h2(SW[11:8],HEX2);
char_7seg h1(SW[7:4],HEX1);
char_7seg h0(SW[3:0],HEX0);
endmodule
//------------------------------------------------------
module char_7seg(sw,hex);
input [3:0]sw;
output [6:0]hex;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off
// ---a----
// | |
// f b
// | |
// ---g----
// | |
// e c
// | |
// ---d----
assign hex= (sw[3:0] == 4'b0000 )? 7'b000_0000: // 0
(sw[3:0] == 4'b0001 )? 7'b111_1001: //1
(sw[3:0] == 4'b0010 )? 7'b010_0100: //2
(sw[3:0] == 4'b0011 )? 7'b011_0000: // 3
(sw[3:0] == 4'b0100 )? 7'b001_1001: // 4
(sw[3:0] == 4'b0101 )? 7'b001_0010: // 5
(sw[3:0] == 4'b0110 )? 7'b000_0010: // 6
(sw[3:0] == 4'b0111 )? 7'b111_1000: // 7
(sw[3:0] == 4'b1000 )? 7'b000_0000: // 8
(sw[3:0] == 4'b1001 )? 7'b001_0000: 7'b111_1111; // 9 - black
endmodule
//----------------------------------------------------------------
Part II
You are to design a circuit that converts a four-bit binary number V = v3v2v1v0 into its two-digit decimal equivalent D = d1d0. Table 1 shows the required output values. A partial design of this circuit is given in Figure 1. Itincludes a comparator that checks when the value of V is greater than 9, and uses the output of this comparator in the control of the 7-segment displays. You are to complete the design of this circuit by creating a Verilog module which includes the comparator, multiplexers, and circuit A (do not include circuit B or the 7-segment decoder at this point). Your Verilog module should have the four-bit input V , the four-bit output M and the output z. The intent of this exercise is to use simple Verilog assign statements to specify the required logic functions using Boolean expressions. Your Verilog code should not include any if-else, case, or similar statements.
Perform the following steps:
1. Make a Quartus II project for your Verilog module.
2. Compile the circuit and use functional simulation to verify the correct operation of your comparator, multiplexers, and circuit A.
3. Augment your Verilog code to include circuit B in Figure 1 as well as the 7-segment decoder. Change the
inputs and outputs of your code to use switches SW30 on the DE2-series board to represent the binary
number V , and the displays HEX1 and HEX0 to show the values of decimal digits d1 and d0. Make sure to
include in your project the required pin assignments for the DE2-series board.
4. Recompile the project, and then download the circuit into the FPGA chip.
5. Test your circuit by trying all possible values of V and observing the output displays.
a b q
0 0 1
0 1 0
1 0 0
1 1 1
q= a'b'+ ab;
code verilog
//-------------------------------------
module eql (
input wire a,b,
output wire q ) ;
wire p0, pl;
assign q = p0 |p1;
assign p0 = ~a & ~b;
assign pl = a & b;
endmodule
//-----------------------------------
* 2-bits comparator
a[1:0] b [1:0] q
00 00 1
00 01 0
00 10 0
00 11 0
01 00 0
01 01 1
01 10 0
01 11 0
10 00 0
10 01 0
10 10 1
10 11 0
11 00 0
11 01 0
11 10 0
11 11 1
q = a[1] 'a[0]'b[1]'b[0]' +a[1]' a[0] b[1]'b[0] +a[1] a[0]'b[1]b[0] '+a[1] a[0]b[1]b[0] ;
code verilog
//--------------------------------------------------
module eq2 (
input wire[1:0] a,b,
output wire q ) ;
wire q3, q2,q1,q0;
assign q = q3|q2|q1|q0;
assign q3 = ( ~a[1] &~ a[0] ) & (~b[1] &~b[0]);
assign q2 = ( ~a[1] & a[0] ) & (~b[1] &b[0]);
assign q1 = ( a[1] &~ a[0] ) & (b[1] &~b[0]);
assign q0 = ( a[1] & a[0] ) & (b[1] &b[0]);
endmodule
//------------------------------------------------
module eq2 (
input wire[1:0] a,b,
output wire q ) ;
wire q1, q0;
eql bit0(a[0], b[0], q0);
eql bit1( a[1], b[1], q1 );
assign q = q0&q1;
endmodule
//-------------------------------------------------
4-bits binary to decimal conversion
//------------------------------------------
module part2(SW,HEX1,HEX0);
input [3:0]SW;
output [6:0]HEX1,HEX0;
wire z ;
wire [3:0]y , m;
wire [2:0]b;
assign y = {1'b0,b};
//-------------------------
comparator compar1(SW[3],SW[2],SW[1],SW[0],z);
circuitA circuita(SW[2:0],b[2:0]);
multi multi1(z,SW[3:0],y,m);
circuitB hex1(z,HEX1);
char_7seg hex0(m , HEX0 );
//-------------------------
endmodule
//------------------------------------------
module comparator(a,b,c,d,q);
input a,b,c,d;
output q ;
wire q5,q4,q3,q2,q1,q0;
assign q = q5|q4|q3|q2|q1|q0;
assign q5 = a&~b&c&~d; //10
assign q4 = a&~b&c&d; //11
assign q3 = a&b&~c&~d; //12
assign q2 = a&b&~c&d; //13
assign q1 = a&b&c&~d; //14
assign q0 = a&b&c&d; //15
endmodule
//-----------------------------------------
module circuitA(a,b);
input [2:0]a;
output [2:0]b;
assign b[2:0] = (a[2:0] == 3'b010) ?3'b000 :
(a[2:0] == 3'b011) ?3'b001 :
(a[2:0] == 3'b100) ?3'b010 :
(a[2:0] == 3'b101) ?3'b011 :
(a[2:0] == 3'b110) ?3'b100 :
(a[2:0] == 3'b111) ?3'b101 :3'b111;
endmodule
//--------------------------------------
module circuitB(a,hex);
input [0:0]a;
output [6:0]hex;
assign hex[6:0] = (a[0] == 1'b1)? 7'b111_1001 : 7'b100_0000; // 1 - 0
endmodule
//-----------------------------------------
module multi(s,x,y,m);
input s;
input [3:0]x,y;
output [3:0]m;
assign m[3] = (~s&x[3] ) | (s&y[3]);
assign m[2] = (~s&x[2] ) | (s&y[2]);
assign m[1] = (~s&x[1] ) | (s&y[1]);
assign m[0] = (~s&x[0] ) | (s&y[0]);
endmodule
//------------------------------------------
module char_7seg(sw,hex);
input [3:0]sw;
output [6:0]hex;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off
// ---a----
// | |
// f b
// | |
// ---g----
// | |
// e c
// | |
// ---d----
assign hex= (sw[3:0] == 4'b0000 )? 7'b000_0000: // 0
(sw[3:0] == 4'b0001 )? 7'b111_1001: //1
(sw[3:0] == 4'b0010 )? 7'b010_0100: //2
(sw[3:0] == 4'b0011 )? 7'b011_0000: // 3
(sw[3:0] == 4'b0100 )? 7'b001_1001: // 4
(sw[3:0] == 4'b0101 )? 7'b001_0010: // 5
(sw[3:0] == 4'b0110 )? 7'b000_0010: // 6
(sw[3:0] == 4'b0111 )? 7'b111_1000: // 7
(sw[3:0] == 4'b1000 )? 7'b000_0000: // 8
(sw[3:0] == 4'b1001 )? 7'b001_0000: 7'b111_1111; // 9 - black
endmodule
//----------------------------------------------------------------
Part III
Figure 2a shows a circuit for a full adder, which has the inputs a, b, and ci , and produces the outputs s and co. Parts b and c of the figure show a circuit symbol and truth table for the full adder, which produces the two-bit binary sum cos = a + b + ci . Figure 2d shows how four instances of this full adder module can be used to design a circuit that adds two four-bit numbers. This type of circuit is usually called a ripple-carry adder, because of the way that the carry signals are passed from one full adder to the next. Write Verilog code that implements this circuit, as described below.
1. Create a new Quartus II project for the adder circuit. Write a Verilog module for the full adder subcircuit
and write a top-level Verilog module that instantiates four instances of this full adder.
2. Use switches SW74 and SW30 to represent the inputs A and B, respectively. Use SW8 for the carry-in
cin of the adder. Connect the SW switches to their corresponding red lights LEDR, and connect the outputs
of the adder, cout and S, to the green lights LEDG.
3. Include the necessary pin assignments for the DE2-series board, compile the circuit, and download it into
the FPGA chip.
4. Test your circuit by trying different values for numbers A, B, and cin.
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