Data Out ==> HEX1:HEX0
//適用於DE2-70 DE2-70
module ROM_Read(
input CLOCK_50, // 50 MHz clock
input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits
output [8:0] LEDG, // LED Green
output [17:0] LEDR, // LED Red
inout [35:0] GPIO_0,GPIO_1, // GPIO Connections
// LCD Module 16X2
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
input UART_RXD, //RS232 RXD
output UART_TXD //RS232 TXD
);
// All inout port turn to tri-state
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
wire clk_25Mout ;
//assign HEX0=7'b111_1111; //off 7-segment Display
//assign HEX1=7'b111_1111;
assign HEX2=7'b111_1111;
assign HEX3=7'b111_1111;
assign HEX4=7'b111_1111;
assign HEX5=7'b111_1111;
assign HEX6=7'b111_1111;
assign HEX7=7'b111_1111;
// Send switches to red leds
assign LEDR = SW;
//Main_ROM_read(Clk,Addr,LCD_DATA);
Main_ROM_read u0(CLOCK_50,SW[5:0],LCD_DATA);
//Max Address 6'd37 Data =8h21 = ASCII "!"
hex_7seg u1(LCD_DATA[3:0],HEX0);
hex_7seg u2(LCD_DATA[7:4],HEX1);
endmodule
module Main_ROM_read(Clk,Addr,LCD_DATA);
input Clk;
input [5:0] Addr;
output reg [7:0]LCD_DATA;
parameter LINE1=5;
parameter NEW_LINE=21;
parameter LINE2=22;
//因為lcd1602每一行可顯示16個Chars，一個 Char 占 8 bits；
parameter [127:0]row1=" hello world!";
parameter [127:0]row2=" I like FPGA!";
always@(posedge Clk)
begin
case (Addr)
0 : LCD_DATA <=(8'h38); //LCD Command
1 : LCD_DATA <=(8'h01);
2 : LCD_DATA <=(8'h06);
3 : LCD_DATA <=(8'h0C);
4 : LCD_DATA <=(8'h80); //LCD DATA LINE 1
LINE1+0 : LCD_DATA <=row1[127:120];
LINE1+1 : LCD_DATA <=row1[119:112];
LINE1+2 : LCD_DATA <=row1[111:104];
LINE1+3 : LCD_DATA <=row1[103:96];
LINE1+4 : LCD_DATA <=row1[95:88];
LINE1+5 : LCD_DATA <=row1[87:80];
LINE1+6 : LCD_DATA <=row1[79:72];
LINE1+7 : LCD_DATA <=row1[71:64];
LINE1+8 : LCD_DATA <=row1[63:56];
LINE1+9 : LCD_DATA <=row1[55:48];
LINE1+10 : LCD_DATA <=row1[47:40];
LINE1+11 : LCD_DATA <=row1[39:32];
LINE1+12 : LCD_DATA <=row1[31:24];
LINE1+13 : LCD_DATA <=row1[23:16];
LINE1+14 : LCD_DATA <=row1[15:8];
LINE1+15 : LCD_DATA <=row1[7:0];
NEW_LINE : LCD_DATA <=(8'hC0); //LCD DATA LINE 2
LINE2+0 : LCD_DATA <=row1[127:120];
LINE2+1 : LCD_DATA <=row1[119:112];
LINE2+2 : LCD_DATA <=row1[111:104];
LINE2+3 : LCD_DATA <=row1[103:96];
LINE2+4 : LCD_DATA <=row1[95:88];
LINE2+5 : LCD_DATA <=row1[87:80];
LINE2+6 : LCD_DATA <=row1[79:72];
LINE2+7 : LCD_DATA <=row1[71:64];
LINE2+8 : LCD_DATA <=row1[63:56];
LINE2+9 : LCD_DATA <=row1[55:48];
LINE2+10 : LCD_DATA <=row1[47:40];
LINE2+11 : LCD_DATA <=row1[39:32];
LINE2+12 : LCD_DATA <=row1[31:24];
LINE2+13 : LCD_DATA <=row1[23:16];
LINE2+14 : LCD_DATA <=row1[15:8];
LINE2+15 : LCD_DATA <=row1[7:0];
default : LCD_DATA <=8'hff;
endcase
end
endmodule
//++++++++++++++++++++++++++++++++++++++
module hex_7seg(hex_digit,seg);
input [3:0] hex_digit;
output [6:0] seg;
reg [6:0] seg;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off
always @ (hex_digit)
case (hex_digit)
4'h0: seg = 7'b1000000;
4'h1: seg = 7'b1111001; // ---a----
4'h2: seg = 7'b0100100; // | |
4'h3: seg = 7'b0110000; // f b
4'h4: seg = 7'b0011001; // | |
4'h5: seg = 7'b0010010; // ---g----
4'h6: seg = 7'b0000010; // | |
4'h7: seg = 7'b1111000; // e c
4'h8: seg = 7'b0000000; // | |
4'h9: seg = 7'b0011000; // ---d----
4'ha: seg = 7'b0001000;
4'hb: seg = 7'b0000011;
4'hc: seg = 7'b1000110;
4'hd: seg = 7'b0100001;
4'he: seg = 7'b0000110;
4'hf: seg = 7'b0001110;
endcase
endmodule
//++++++++++++++++++++++++++++++++++++++
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