計數器是能根據輸入脈衝而產生一連串預定順序狀態的暫存器，所以計數器也是由正反器所構成。一個四位元二進位漣波計數器是由ＪＫ正反器的補數運算所構成，每個正反器的輸出的都依序連到下一個正反器的Ck輸入，儲存最低有效位元的正反器所接受的是計數脈衝。所有正反器的Ｊ與Ｋ兩輸入都恆接到邏輯１。
源自於http://www.electronics-tutorials.ws/counter/count_2.html
Asynchronous Counter
In the previous tutorial we saw that an Asynchronous counter can have 2n-1 possible counting states e.g. MOD-16 for a 4-bit counter, (0-15) making it ideal for use in Frequency Division. But it is also possible to use the basic asynchronous counter to construct special counters with counting states less than their maximum output number by forcing the counter to reset itself to zero at a pre-determined value producing a type of asynchronous counter that has truncated sequences. Then an n-bit counter that counts up to its maximum modulus (2n) is called a full sequence counter and a n-bit counter whose modulus is less than the maximum possible is called a truncated counter.
But why would we want to create an asynchronous truncated counter that is not a MOD-4, MOD-8, or some other modulus that is equal to the power of two. The answer is that we can by using combinational logic to take advantage of the asynchronous inputs on the flip-flop. If we take the modulo-16 asynchronous counter and modified it with additional logic gates it can be made to give a decade (divide-by-10) counter output for use in standard decimal counting and arithmetic circuits.
Such counters are generally referred to as Decade Counters. A decade counter requires resetting to zero when the output count reaches the decimal value of 10, ie. when DCBA = 1010 and to do this we need to feed this condition back to the reset input. A counter with a count sequence from binary "0000" (BCD = "0") through to "1001" (BCD = "9") is generally referred to as a BCD binary-coded-decimal counter because its ten state sequence is that of a BCD code but binary decade counters are more common.
Asynchronous Decade Counter
This type of asynchronous counter counts upwards on each leading edge of the input clock signal starting from "0000" until it reaches an output "1010" (decimal 10). Both outputs QB and QD are now equal to logic "1" and the output from the NAND gate changes state from logic "1" to a logic "0" level and whose output is also connected to the CLEAR (CLR) inputs of all the J-K Flip-flops.
This signal causes all of the Q outputs to be reset back to binary "0000" on the count of 10. Once QB andQD are both equal to logic "0" the output of the NAND gate returns back to a logic level "1" and the counter restarts again from "0000". We now have a decade or Modulo-10 counter.
Decade Counter Truth Table
| Clock Count | Output bit Pattern | Decimal Value | |||
| QD | QC | QB | QA | ||
| 1 | 0 | 0 | 0 | 0 | 0 |
| 2 | 0 | 0 | 0 | 1 | 1 |
| 3 | 0 | 0 | 1 | 0 | 2 |
| 4 | 0 | 0 | 1 | 1 | 3 |
| 5 | 0 | 1 | 0 | 0 | 4 |
| 6 | 0 | 1 | 0 | 1 | 5 |
| 7 | 0 | 1 | 1 | 0 | 6 |
| 8 | 0 | 1 | 1 | 1 | 7 |
| 9 | 1 | 0 | 0 | 0 | 8 |
| 10 | 1 | 0 | 0 | 1 | 9 |
| 11 | Counter Resets its Outputs back to Zero | ||||
Decade Counter Timing Diagram
Using the same idea of truncating counter output sequences, the above circuit could easily be adapted to other counting cycles be simply changing the connections to the AND gate. For example, a scale-of-twelve (modulo-12) can easily be made by simply taking the inputs to the AND gate from the outputs at "QC" and "QD", noting that the binary equivalent of 12 is "1100" and that output "QA" is the least significant bit (LSB).
Since the maximum modulus that can be implemented with n flip-flops is 2n, this means that when you are designing truncated asynchronous counters you should determine the lowest power of two that is greater than or equal to your desired modulus. For example, lets say you wish to count from 0 to 39, or mod-40. Then the highest number of flip-flops required would be six, n = 6 giving a maximum MOD of 64 as five flip-flops would only equal MOD-32.
Now suppose we wanted to build a "divide-by-128" counter for frequency division we would need to cascade seven flip-flops since 128 = 27. Using dual flip-flops such as the 74LS74 we would still need four IC's to complete the circuit.
One easy alternative method would be to use two TTL 7493's as 4-bit ripple counter/dividers. Since 128 = 16 x 8, one 7493 could be configured as a "divide-by-16" counter and the other as a "divide-by-8" counter. The two IC's would be cascaded together to form a "divide-by-128" frequency divider as shown.
Of course standard IC asynchronous counters are available such as the TTL 74LS90 programmable ripple counter/divider which can be configured as a divide-by-2, divide-by-5 or any combination of both. The 74LS390 is a very flexible dual decade driver IC with a large number of "divide-by" combinations available ranging form divide-by-2, 4, 5, 10, 20, 25, 50, and 100.
// Ch08 cnt6.v
// 三位元漣波計數器
module cnt6(SW, LEDR, LEDG , CLOCK_27 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3 ,HEX4 );
input [17:0] SW; // toggle switches
input [3:0] KEY; // Push bottom
input CLOCK_27; //Clock 27MHz , 50Mhz
output [17:0] LEDR; // red LEDS
output [8:0] LEDG; // green LEDs
output [6:0] HEX0,HEX1,HEX2,HEX3 ,HEX4; //7-segment display
//set original program input , output
//module cnt6 (Clk,Clr,Q);
//input Clk,Clr; // 一位元輸入
//output [2:0] Q; // 三位元輸出
//reg [2:0] Q; // 宣告為暫存器資料
wire Clk,Clr; // 一位元輸入
reg [3:0] Q; // 宣告為暫存器資料
wire [7:0] segout0; //HEX 0
assign Clk=KEY[0];
assign Clr=KEY[1];
assign LEDG[1:0]=KEY[1:0];
// 上緣觸發時脈, 上緣同步清除, T 型正反器
always@ (negedge Clk or negedge Clr) // 時脈為上緣觸發 Clk
if (!Clr) Q[0] = 0;
else Q[0] = ~Q[0];
always@ (negedge Q[0] or negedge Clr) // 時脈為下緣觸發 Q[0]
if (!Clr) Q[1] = 0;
else Q[1] = ~Q[1];
always@ (negedge Q[1] or negedge Clr) // 時脈為下緣觸發 Q[1]
if (!Clr) Q[2] = 0;
else Q[2] = ~Q[2];
always@ (negedge Q[2] or negedge Clr) // 時脈為下緣觸發 Q[1]
if (!Clr) Q[3] = 0;
else Q[3] = ~Q[3];
_7seg UUT0(.hex(Q),
.seg(segout0));
assign HEX0=segout0[6:0];
assign LEDG[7:4]=Q;
endmodule
//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//-----------------------------------------
module _7seg(hex , seg);
input [3:0] hex;
output [7:0] seg;
reg [7:0] seg;
// segment encoding
// 0
// ---
// 5 | | 1
// --- <- 6
// 4 | | 2
// ---
// 3
always @(hex)
begin
case (hex)
// Dot point is always disable
4'b0001 : seg = 8'b11111001; //1 = F9H
4'b0010 : seg = 8'b10100100; //2 = A4H
4'b0011 : seg = 8'b10110000; //3 = B0H
4'b0100 : seg = 8'b10011001; //4 = 99H
4'b0101 : seg = 8'b10010010; //5 = 92H
4'b0110 : seg = 8'b10000010; //6 = 82H
4'b0111 : seg = 8'b11111000; //7 = F8H
4'b1000 : seg = 8'b10000000; //8 = 80H
4'b1001 : seg = 8'b10010000; //9 = 90H
4'b1010 : seg = 8'b10001000; //A = 88H
4'b1011 : seg = 8'b10000011; //b = 83H
4'b1100 : seg = 8'b11000110; //C = C6H
4'b1101 : seg = 8'b10100001; //d = A1H
4'b1110 : seg = 8'b10000110; //E = 86H
4'b1111 : seg = 8'b10001110; //F = 8EH
default : seg = 8'b11000000; //0 = C0H
endcase
end
endmodule
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