HBLbits_Verilog More Verilog Features

 HBLbits_Verilog More Verilog Features

More Verilog Features

·        Conditional ternary operator

·        Reduction operators

·        Reduction: Even wider gates

·        Combinational for-loop: Vector reversal 2

·        Combinational for-loop: 255-bit population count

·        Generate for-loop: 100-bit binary adder 2

·        Generate for-loop: 100-digit BCD adder

Conditional

Verilog has a ternary conditional operator ( ? : ) much like C:

(condition ? if_true : if_false)

Examples: (0 ? 3 : 5)     // This is 5 because the condition is false. (sel ? b : a)   // A 2-to-1 multiplexer between a and b selected by sel.   always @(posedge clk)         // A T-flip-flop.   q <= toggle ? ~q : q;   always @(*)                   // State transition logic for a one-input FSM   case (state)     A: next = w ? B : A;     B: next = w ? A : B;   endcase   assign out = ena ? q : 1'bz;  // A tri-state buffer   ((sel[1:0] == 2'h0) ? a :     // A 3-to-1 mux  (sel[1:0] == 2'h1) ? b :                       c )

Given four unsigned numbers, find the minimum. 

 

module top_module (     input [7:0] a, b, c, d,     output [7:0] min);//       // assign intermediate_result1 = compare? true: false;     assign min= (a<=b && a<=c && a<=d) ? a:         (b<=a && b<=c && b<=d) ?  b:         (c<=a && c<=b && c<=d) ? c :  d ; endmodule

Reduction

The reduction operators can do AND, OR, and XOR of the bits of a vector, producing one bit of output:

& a[3:0]     // AND: a[3]&a[2]&a[1]&a[0]. Equivalent to (a[3:0] == 4'hf)

| b[3:0]     // OR:  b[3]|b[2]|b[1]|b[0]. Equivalent to (b[3:0] != 4'h0)

^ c[2:0]     // XOR: c[2]^c[1]^c[0]

Parity checking is often used as a simple method of detecting errors when transmitting data through an imperfect channel.

We will use "even" parity, where the parity bit is just the XOR of all 8 data bits.

module top_module (     input [7:0] in,     output parity);     assign parity = in[7]^in[6]^in[5]^in[4]^in[3]^in[2]^in[1]^in[0]; endmodule

Gates100

 

Build a combinational circuit with 100 inputs, in[99:0].

There are 3 outputs:

·        out_and: output of a 100-input AND gate.

·        out_or: output of a 100-input OR gate.

·        out_xor: output of a 100-input XOR gate.

 

module top_module(     input [99:0] in,     output out_and,     output out_or,     output out_xor );     assign out_and =  & in;     assign out_or =   | in;     assign out_xor =  ^ in;   endmodule

Vector100r

Given a 100-bit input vector [99:0], reverse its bit ordering.

module top_module(     input [99:0] in,     output [99:0] out );     integer i;     always@(*)begin         for(i = 0; i <= 99; i = i + 1)begin             out[i] = in[99 - i];         end     end   endmodule

Popcount255

A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 255-bit input vector.

module top_module(     input [254:0] in,     output [7:0] out );     integer i;     always@(*) begin         out = 8'd0;         for(i=0;i<=254;i=i+1) begin                  out=out+in[i];             end     end endmodule

Adder100i

 

Create a 100-bit binary ripple-carry adder by instantiating 100 full adders.

module top_module(     input [99:0] a, b,     input cin,     output [99:0] cout,     output [99:0] sum );         integer i;     always@(*) begin             for(i=0; i<=99; i=i+1)begin                 if(i==0)                 {cout[i],sum[i]}=a[i]+b[i]+cin;             else                     {cout[i],sum[i]}=a[i]+b[i]+cout[i-1];            end     end        endmodule

 

Bcdadd100

 

with a BCD one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.

module bcd_fadd {

    input [3:0] a,

    input [3:0] b,

    input     cin,

    output   cout,

    output [3:0] sum );

Instantiate 100 copies of bcd_fadd to create a 100-digit BCD ripple-carry adder.

generate語法 ·        定義genvar，作為generate種的迴圈變數。 ·        generate語句中定義的for語句，必須要有begin，為後續增加標籤做準備。 ·        begin必須要有名稱，也就是必須要有標籤，因為標籤會作為generate迴圈的實例名稱。 ·        可以使用在generate語句中的類型主要有： o     module（模組） o     UDP（用戶自訂原語） o     Gate level門級原語 o     連續賦值（continuous assignment）陳述式 o     initial或always語句 ·        基本結構如下： genvar 迴圈變數名； generate     // generate迴圈語句     // generate 條件陳述式     // generate 分支語句     // 嵌套的generate語句 endgenerate

 

module top_module(     input [399:0] a, b,     input cin,     output cout,     output [399:0] sum );           /*module bcd_fadd {input [3:0]a,input [3:0]b,     input cin,output cout,output[3:0] sum );*/     wire [99:0]c_tmp;     bcd_fadd u0(a[3:0],b[3:0],cin,c_tmp[0],sum[3:0]);         generate     genvar i;          for(i=1;i<=99;i=i+1)begin:adder                 bcd_fadd ui_bcd_fadd(                     .a             (a[4 * i + 3: 4 * i]    ),                     .b             (b[4 * i + 3: 4 * i]    ),                     .cin  (c_tmp[i - 1]          ),                     .sum        (sum[4 * i + 3: 4 * i]  ),                     .cout        (c_tmp[i]              )                 );             end         endgenerate     assign cout = c_tmp[99];    endmodule