HBLbits_Verilog Modules: Hierarchy

HBLbits_Verilog Modules: Hierarchy

Modules: Hierarchy

·        Modules

·        Connecting ports by position

·        Connecting ports by name

·        Three modules

·        Modules and vectors

·        Adder 1

·        Adder 2

·        Carry-select adder

·        Adder-subtractor

Module

module mod_a ( input in1, input in2, output out );

    // Module body

endmodule

Connecting Signals to Module Ports

By position

mod_a instance1 ( wa, wb, wc );

By name

mod_a instance2 ( .out(wc), .in1(wa), .in2(wb) );

module top_module ( input a, input b, output out );

    //mod_a u1(a,b,out);  //by position

    mod_a u2(.in1(a),.in2(b), .out(out)); //By name

endmodule

Module pos

module mod_a ( output, output, input, input, input, input );

 

module top_module (

    input a,

    input b,

    input c,

    input d,

    output out1,

    output out2

);

//mod_a ( output, output, input, input, input, input );

    mod_a ( out1, out2, a, b, c, d );

endmodule

 

Module name

6 ports by name to your top-level module's ports:

Port in mod_a	Port in top_module
output out1	out1
output out2	out2
input in1	a
input in2	b
input in3	c
input in4	d

You are given the following module:

module mod_a ( output out1, output out2, input in1, input in2, input in3, input in4);

 

module top_module (

    input a,

    input b,

    input c,

    input d,

    output out1,

    output out2

);

//module mod_a ( output out1, output out2, input in1, input in2, input in3, input in4);

    mod_a u1( .out1(out1), .out2(out2), .in1(a), .in2(b), .in3(c), .in4(d));

endmodule

 

Module shift

module my_dff ( input clk, input d, output q );

module top_module ( input clk, input d, output q );

    //module my_dff ( input clk, input d, output q );

    wire q1,q2;

    my_dff u1(.clk(clk),.d(d),.q(q1));

    my_dff u2(.clk(clk),.d(q1),.q(q2));

    my_dff u3(.clk(clk),.d(q2),.q(q)); 

                       

endmodule

 

module top_module (

        input clk,

        input d,

        output q

);

 

        wire a, b; // Create two wires. I called them a and b.

 

        // Create three instances of my_dff, with three different instance names (d1, d2, and d3).

        // Connect ports by position: ( input clk, input d, output q)

        my_dff d1 ( clk, d, a );

        my_dff d2 ( clk, a, b );

        my_dff d3 ( clk, b, q );

 

endmodule

 

 

Module shift8

4-to-1 multiplexer (not provided)

The module provided to you is: module my_dff8 ( input clk, input [7:0] d, output [7:0] q );

module top_module (

    input clk,

    input [7:0] d,

    input [1:0] sel,

    output [7:0] q

);

    wire[7:0] q1,q2,q3;

    //module my_dff8 ( input clk, input [7:0] d, output [7:0] q );

    my_dff8 u1( clk,  d, q1);

    my_dff8 u2( clk, q1, q2);

    my_dff8 u3( clk, q2, q3);

    always@(d,sel) begin

        case (sel)

                 2'b00: q=d;

            2'b01: q=q1;

            2'b10: q=q2;

            2'b11: q=q3;

        endcase

    end

   

endmodule

 

Module add

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

 module top_module(

    input [31:0] a,

    input [31:0] b,

    output [31:0] sum

);

     wire c0,c1;

//module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

    add16 u1(a[15:0],b[15:0],1'b0,sum[15:0],c0);

    add16 u2(a[31:16],b[31:16],c0,sum[31:16],c1);

endmodule

 

Module fadd

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

 

module add1 ( input a, input b, input cin, output sum, output cout );

Recall that a full adder computes the sum and carry-out of a+b+cin.

In summary, there are three modules in this design:

·        top_module — Your top-level module that contains two of...

·        add16, provided — A 16-bit adder module that is composed of 16 of...

·        add1 — A 1-bit full adder module.

module top_module (

    input [31:0] a,

    input [31:0] b,

    output [31:0] sum

);//

    wire c0,c1;

//add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

    add16 u1(a[15:0],b[15:0],1'b0,sum[15:0],c0);

    add16 u2(a[31:16],b[31:16],c0,sum[31:16],c1);

endmodule

 

 

module add1 ( input a, input b, input cin,   output sum, output cout );

// Full adder module here

    assign {cout,sum}=a+b+cin;

endmodule

Module cseladd

module  add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

module top_module(

    input [31:0] a,

    input [31:0] b,

    output [31:0] sum

);

    wire c0,c1,c2;

    wire [15:0] sum_temp1,sum_temp2;

//add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

    add16 u1(a[15:0],b[15:0],1'b0,sum[15:0],c0);

    add16 u2(a[31:16],b[31:16],1'b0,sum_temp1,c1);

    add16 u3(a[31:16],b[31:16],1'b1,sum_temp2,c2);

    always@(*) begin

        case(c0)

            1'b0: sum[31:16]=sum_temp1;

            1'b1: sum[31:16]=sum_temp2;

        endcase

   end

endmodule

Module addsub

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

module top_module(

    input [31:0] a,

    input [31:0] b,

    input sub,

    output [31:0] sum

);

    wire c0,c1;

    wire [31:0]b_data;

//add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

    add16 u1 ( a[15:0],b_data[15:0], sub, sum[15:0], c0 );

    add16 u2 ( a[31:16],b_data[31:16], c0, sum[31:16], c1 );

    always@(*) begin

        case (sub)

            1'b0: b_data=b;

            1'b1: b_data=b[31:0] ^ 32'hffff_ffff;

        endcase

    end

endmodule