HBLbits_Verilog Basic_Exams/review2015 fsmshift

HBLbits_Verilog Basic_Exams/review2015 fsmshift

FSM: Enable shift register（Exams/review2015 fsmshift）

This is the third component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.

As part of the FSM for controlling the shift register, we want the ability to enable the shift register for exactly 4 clock cycles whenever the proper bit pattern is detected. We handle sequence detection in Exams/review2015_fsmseq, so this portion of the FSM only handles enabling the shift register for 4 cycles.

Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset).

//方法1，状态机思想
module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);

    parameter S0=0,S1=1,S2=2,S3=3,S4=4;
    reg [2:0]state,next;

    always@(posedge clk)
    if(reset)
            state <= S0;
    else
        state <= next;

    always@(*)
        case(state)
            S0:next=S1;
            S1:next=S2;
            S2:next=S3;
            S3:next=S4;
            S4:next=S4;
            default:next=S0;
        endcase

    assign shift_ena=(state==S0|state==S1|state==S2|state==S3);
endmodule

//第二种做法，计数器
module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);

    reg [9:0] cnt_4;
    //cnt_4(4次计数器)
    always@(posedge clk)
    if(reset)
        cnt_4 <= 'd0;
    else
        cnt_4 <= cnt_4 + 1'b1;

    assign shift_ena = cnt_4 < 'd4;

endmodule

//第三种做法：强烈推荐这种，理解计数器什么时候加，什么时候结束加！（我记得明德扬之前讲，经常是这种思路）
module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);

    reg [9:0] cnt_4;//cnt_4(4次计数器)
    wire cnt_end;

    always@(posedge clk)
        if(reset)
            cnt_4 <= 'd0;
        else if(shift_ena)
            cnt_4 <= cnt_4 + 1'b1;
        else
            cnt_4 <= 'd0;

    assign cnt_end = shift_ena && (cnt_4 == 'd3);

    always@(posedge clk)
        if(reset)
            shift_ena <= 1'b1;
        else if(cnt_end)
            shift_ena <= 1'b0;
endmodule