HBLbits_Verilog Arithmetic

HBLbits_Verilog Arithmetic

Arithmetic Circuits

·        Half adder

·        Full adder

·        3-bit binary adder

·        Adder

·        Signed addition overflow

·        100-bit binary adder

·        4-digit BCD adder

Hadd

Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out.

 

module top_module(     input a, b,     output cout, sum );     assign {cout,sum}= a+b; endmodule

Fadd

Create a full adder. A full adder adds three bits (including carry-in) and produces a sum and carry-out.

module top_module(     input a, b, cin,     output cout, sum );     assign {cout,sum}= a+b +cin; endmodule

Adder3

Now that you know how to build a full adder, make 3 instances of it to create a 3-bit binary ripple-carry adder. The adder adds two 3-bit numbers and a carry-in to produce a 3-bit sum and carry out. 

module top_module(     input [2:0] a, b,     input cin,     output [2:0] cout,     output [2:0] sum );     fadd u0(a[0],b[0],cin,cout[0],sum[0]);     fadd u1(a[1],b[1],cout[0],cout[1],sum[1]);     fadd u2(a[2],b[2],cout[1],cout[2],sum[2]); endmodule   module fadd(     input a, b, cin,     output cout, sum );     assign {cout,sum}= a+b +cin; endmodule

 

module top_module(     input [2:0] a, b,     input cin,     output [2:0] cout,     output [2:0] sum );     integer i;     always@(*)begin         for(i = 0; i <= 2; i = i + 1)begin             if(i == 0)begin                 cout[i] = a[i] & b[i] | a[i] & cin | b[i] & cin;                 sum[i] = a[i] ^ b[i] ^ cin;             end             else begin                 cout[i] = a[i] & b[i] | a[i] & cout[i - 1] | b[i] & cout[i - 1];                 sum[i] = a[i] ^ b[i] ^ cout[i - 1];             end         end     end   endmodule

Exams/m2014 q4j

Implement the following circuit:

module top_module (     input [3:0] x,     input [3:0] y,     output [4:0] sum);     wire [3:0]c_tmp;     fa u0(x[0],y[0],1'b0,c_tmp[0],sum[0]);     fa u1(x[1],y[1],c_tmp[0],c_tmp[1],sum[1]);     fa u2(x[2],y[2],c_tmp[1],c_tmp[2],sum[2]);     fa u3(x[3],y[3],c_tmp[2],sum[4],sum[3]);  endmodule         module fa(     input x,     input y,     input cin,     output cout,     output sum);     assign {cout,sum}=x+y+cin;    endmodule

 

module top_module (         input [3:0] x,         input [3:0] y,         output [4:0] sum );           // This circuit is a 4-bit ripple-carry adder with carry-out.         assign sum = x+y;   // Verilog addition automatically produces the carry-out bit.           // Verilog quirk: Even though the value of (x+y) includes the carry-out, (x+y) is still considered to be a 4-bit number (The max width of the two operands).         // This is correct:         // assign sum = (x+y);         // But this is incorrect:         // assign sum = {x+y};     // Concatenation operator: This discards the carry-out endmodule

Exams/ece241 2014 q1c

Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred.

 

module top_module (     input [7:0] a,     input [7:0] b,     output [7:0] s,     output overflow ); //       // assign s = ...     // assign overflow = ...    assign s = a + b;    assign overflow = a[7] & b[7] & ~s[7] | ~a[7] & ~b[7] & s[7];   endmodule

 

module top_module (     input [7:0] a,     input [7:0] b,     output [7:0] s,     output overflow ); //          wire [7:0]c_tmp;     fa u0(a[0],b[0],1'b0,c_tmp[0],s[0]);     fa u1(a[1],b[1],c_tmp[0],c_tmp[1],s[1]);     fa u2(a[2],b[2],c_tmp[1],c_tmp[2],s[2]);        fa u3(a[3],b[3],c_tmp[2],c_tmp[3],s[3]);        fa u4(a[4],b[4],c_tmp[3],c_tmp[4],s[4]);        fa u5(a[5],b[5],c_tmp[4],c_tmp[5],s[5]);     fa u6(a[6],b[6],c_tmp[5],c_tmp[6],s[6]);       fa u7(a[7],b[7],c_tmp[6],c_tmp[7],s[7]);     assign overflow= c_tmp[6] ^ c_tmp[7] ; endmodule module fa(     input x,     input y,     input cin,     output cout,     output sum);     assign {cout,sum}=x+y+cin;    endmodule

Adder100

 

Create a 100-bit binary adder. The adder adds two 100-bit numbers and a carry-in to produce a 100-bit sum and carry out.

module top_module(     input [99:0] a, b,     input cin,     output cout,     output [99:0] sum );       assign {cout, sum} = a + b  + cin;   endmodule

 

module top_module(     input [99:0] a, b,     input cin,     output cout,     output [99:0] sum );       integer i;     wire [100:0] c_tmp;     assign c_tmp[0]=cin;     always@(*) begin         for (i=0;i<=99;i=i+1) begin             {c_tmp[i+1],sum[i]}=a[i]+b[i]+c_tmp[i];         end         cout=c_tmp[100];     end endmodule

Bcdadd4

You are provided with a BCD (binary-coded decimal) one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.

module bcd_fadd {

    input [3:0] a,

    input [3:0] b,

    input     cin,

    output   cout,

    output [3:0] sum );

Instantiate 4 copies of bcd_fadd to create a 4-digit BCD ripple-carry adder. 

module top_module(     input [15:0] a, b,     input cin,     output cout,     output [15:0] sum );       /*module bcd_fadd {     input [3:0] a,     input [3:0] b,     input     cin,     output   cout,     output [3:0] sum );    */     wire [2:0]c_tmp;     bcd_fadd u0 (a[3:0],b[3:0],cin,c_tmp[0],sum[3:0]);     bcd_fadd u1 (a[7:4],b[7:4],c_tmp[0],c_tmp[1],sum[7:4]);     bcd_fadd u2 (a[11:8],b[11:8],c_tmp[1],c_tmp[2],sum[11:8]);     bcd_fadd u3 (a[15:12],b[15:12],c_tmp[2],cout,sum[15:12]); endmodule