DE2-115 開發 以 Tri-State gate 74125/74126 為例(Verilog data flow modeling )

 DE2-115 開發 以 Tri-State  gate 74125/74126  為例(Verilog  data flow modeling )

//Tirstate_Buffer_74126 74125

module Tirstate_Buffer_74126(SW, LEDR, LEDG , CLOCK_50 ,KEY,HEX0 ,HEX1 ,HEX2,HEX3 ,HEX4 ,HEX5 ,HEX6 ,HEX7 );

 input  [17:0] SW;   // toggle switches

 input  [3:0] KEY;   // Push bottom

 input  CLOCK_50;    //Clock 27MHz , 50Mhz

 output [17:0] LEDR;   // red  LEDS

 output [8:0] LEDG;   // green LEDs

 output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7 ; //7-segment display

 assign HEX0=7'b111_1111; //off 7-segment Display

 assign HEX1=7'b111_1111;

 assign HEX2=7'b111_1111;   //off 7-segment Display

 assign HEX3=7'b111_1111;

 assign HEX4=7'b111_1111;

 assign HEX5=7'b111_1111;

 assign HEX6=7'b111_1111;

 assign HEX7=7'b111_1111;

 tri_buf_74126 u1(SW[0],LEDR[0],KEY[0]);

 tri_buf_74126 u2(SW[2],LEDR[2],KEY[1]);

 

 tri_buf_74125 u3(SW[4],LEDR[4],KEY[2]);

 tri_buf_74125 u4(SW[6],LEDR[6],KEY[3]);

 

endmodule

module tri_buf_74126 (a,b,enable);

 input a;

 output b;

 input enable;

 wire b;

 assign b = (enable) ? a : 1'bz;

     

endmodule

module tri_buf_74125 (a,b,enable);

 input a;

 output b;

 input enable;

 wire b;

 assign b = (~enable) ? a : 1'bz;

    

endmodule