DE2-115 開發 以 4bit comparator 7485 為例(Verilog behavioral modeling )

 DE2-115 開發 以 4bit comparator  7485 為例(Verilog behavioral modeling )

module Comparator_4bit(SW, LEDR, LEDG , CLOCK_50 ,KEY,HEX0 ,HEX1 ,HEX2,HEX3 ,HEX4 ,HEX5 ,HEX6 ,HEX7 );

 input  [17:0] SW;   // toggle switches

 input  [3:0] KEY;   // Push bottom

 input  CLOCK_50;    //Clock 27MHz , 50Mhz

 output [17:0] LEDR;   // red  LEDS

 output [8:0] LEDG;   // green LEDs

 output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7 ; //7-segment display

 assign HEX0=7'b111_1111; //off 7-segment Display

 assign HEX1=7'b111_1111;

 assign HEX2=7'b111_1111;   //off 7-segment Display

 assign HEX3=7'b111_1111;

 assign HEX4=7'b111_1111;

 assign HEX5=7'b111_1111;

 assign HEX6=7'b111_1111;

 assign HEX7=7'b111_1111;

comparator(SW[3:0],SW[7:4],LEDR[0],LEDR[1],LEDR[2]);

endmodule

//declare the Verilog module - The inputs and output signals.

module comparator(

    Data_in_A,  //input A

    Data_in_B,  //input B

    less,       //high when A is less than B

    equal,       //high when A is equal to B

    greater         //high when A is greater than B    

    );

    //what are the input ports.

    input [3:0] Data_in_A;

    input [3:0] Data_in_B;

    //What are the output ports.

    output less;

    output equal;

    output greater;

    //Internal variables

    reg less;

    reg equal;

    reg greater;

    //When the inputs and A or B are changed execute this block

    always @(Data_in_A or Data_in_B)

     begin

        if(Data_in_A > Data_in_B)   begin  //check if A is bigger than B.

            less = 0;

            equal = 0;

            greater = 1;    end

        else if(Data_in_A == Data_in_B) begin //Check if A is equal to B

            less = 0;

            equal = 1;

            greater = 0;    end

        else    begin //Otherwise - check for A less than B.

            less = 1;

            equal = 0;

            greater =0;

        end 

    end

endmodule