P7-13 以8bit Odd Parity 產生16bit Odd Parity Checker 適用於DE2-70

P7-13 以8bit Odd Parity 產生16bit Odd Parity Checker 

適用於DE2-70

//-----------------------------------------------

// 16-bit odd-parity generator using two 8-bit 

// odd-parity generators

// Filename : odd_parity_16.v

//-----------------------------------------------

module odd_parity (SW, LEDR, LEDG , CLOCK_27 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3 );

 input  [17:0] SW;   // toggle switches

 input  [7:0] KEY;       // Push bottom

 input  CLOCK_27;   //Clock 27MHz , 50Mhz

 output [17:0] LEDR;   // red  LEDS   

   output [8:0] LEDG;   // green LEDs

    

    output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display

    

  

 //set original program input , output 

 //(Din, Pout);

 //input [15:0] Din;

 //output Pout;

  

 wire [15:0] Din;

 reg [7:0] High_byte; // Hight byte of input data

 reg [7:0] Low_byte;  // Low byte of input data

 reg High, Low;       // Parities of high and low byte

 reg Pout;         // Parity output

 assign Din=SW[15:0];

 assign LEDR[15:0]=SW[15:0];

  always @(Din)

    begin

      High_byte = Din[15:8];

    Low_byte = Din[7:0];

odd8(High_byte, High);

odd8(Low_byte, Low);

Pout = High ~^ Low; // Bitwise xnor

    end

  assign LEDG[0]=Pout; 

  

//================================== 

task odd8;

  input [7:0] I;

  output odd8;

  begin 

   odd8 = ~^ I; // reduction xnor operation

  end

endtask

endmodule