bufif0及bufif1建立之4對1多工器

bufif0及bufif1建立之4對1多工器Verilong程式

module mux4_1(s, i, y);

  input [1:0]s;

  input [3:0]i;

  output y;

  wire y0,y1;

  bufif0(y0,i[0],s[0]);

  bufif1(y0,i[1],s[0]);

  bufif0(y1,i[2],s[0]);

  bufif1(y1,i[3],s[0]);

  bufif0(y,y0,s[1]);

  bufif1(y,y1,s[1]);

endmodule

//============================

`timescale 1ns / 1ps

module testbench;

        reg [1:0] s=0;  // Inputs

        reg [3:0] i=0;

        wire  y;     // Outputs

        // Instantiate the Unit Under Test (UUT)

        zaq uut (.s(s),.i(i),.y(y) );

        initial begin

                #200 s=00;i=0001;

                #200 s=01;i=0010;

                #200 s=10;i=0100;

                #200 s=11;i=1000;

                #200 s=00;i=0001;

        end

   initial #1000 $finish;

 initial $monitor("Time = %3g,s = %b,i = %b,y = %4b",$time,s,i,y);

endmodule