Verilog HDL: Test Bench for 4 bit Counter

源自http://asic-soc.blogspot.tw/2012/06/verilog-hdl-test-bench-for-4-bit.html

Verilog HDL: Test Bench for 4 bit Counter

Test Bench for 4 bit Counter:

module tb_4bitcounter

reg tclk,trst;

wire [3:0]tq;

counter_4bit C1(.tq(q), .tclk(clk), .trst(rst)); instantiate counter to be tested.

initial

begin

#0 trst=1’b0; //tclk=1’b?;

#5 trst=1’b1; //tclk=1’b1;

#100 trst=1’b1; //tclk=1’b0;

end

tclk=1’b0; //tclk=1’b0;

#10 tclk=1’b1; //forever

#20 tclk=1’b0; //#10 tclk=~tclk;

end        //end

endmodule

initial

#500 $stop;

end

initial

$monitor
(trst=%b, tclk=%b, tq=%d “, trst, tclk,tq)

end

Another way:

module tb_4bitcounter

reg tclk,trst,ten;

wire [3:0] tq;

initial

tclk=1’b0;

always

#20 tclk=~tclk; //generate clock

initial

trst=1’b1; //generate reset signal

#20 trst=1’b0;

#700 trst=1’b1;

end

counter_4bit C1(.tq(q), .tclk(clk), .trst(rst)); //instantiate counter to be tested.

$monitor
(trst=%b, tclk=%b, tq=%d “, trst, tclk,tq)

endmodulealways  //initial