8-Bit Up-Down Counter

		源自http://www.asic-world.com/examples/verilog/up_down_counter.html
		8-Bit Up-Down Counter 1 //----------------------------------------------------- 2 // Design Name : up_down_counter 3 // File Name : up_down_counter.v 4 // Function : Up down counter 5 // Coder : Deepak Kumar Tala 6 //----------------------------------------------------- 7 module up_down_counter ( 8 out , // Output of the counter 9 up_down , // up_down control for counter 10 clk , // clock input 11 data , // Data to load 12 reset // reset input 13 ); 14 //----------Output Ports-------------- 15 output [7:0] out; 16 //------------Input Ports-------------- 17 input [7:0] data; 18 input up_down, clk, reset; 19 //------------Internal Variables-------- 20 reg [7:0] out; 21 //-------------Code Starts Here------- 22 always @(posedge clk) 23 if (reset) begin // active high reset 24 out <= 8'b0 ; 25 end else if (up_down) begin 26 out <= out + 1; 27 end else begin 28 out <= out - 1; 29 end 30 31 endmodule