/*
SW[0] PIN_N25 --> J
SW[1] PIN_N26 --> K
LEDR[0] PIN_AE23 -->Q
LEDR[1] PIN_AF23 -->Qbar
KEY[0] PIN_G26 --> Clk
*/
module JK_FF (
input J,K,Clk ,
output reg Q ,
output Qbar=1'b1 ); // 宣告輸入輸出
always @ (negedge Clk)
begin
if (J == 0 && K == 0) // No change
Q <= Q;
else if (J == 0 && K == 1) // Clear
Q <= 0;
else if (J == 1 && K == 0) // Set
Q <= 1;
else if (J == 1 && K == 1) // Complement
Q <= Qbar;
end // always
assign Qbar = ~Q;
endmodule
/*
SW[0] PIN_N25 --> J
SW[1] PIN_N26 --> K
LEDR[0] PIN_AE23 -->Q
LEDR[1] PIN_AF23 -->Q_bar
KEY[0] PIN_G26 --> Clk
*/
沒有留言:
張貼留言