Four-Bit Adder in Verilog

Xilinx ISE Four-Bit Adder in Verilog

http://cs.smith.edu/dftwiki/index.php/Xilinx_ISE_Four-Bit_Adder_in_Verilog

--D. Thiebaut 11:03, 24 April 2012 (EDT)

---

	This lab should be done after the introduction lab on Verilog. It shows how to use two modules, one for the basic 3-bit full-adder (adding a to b with carry-in), and one that uses 4 of them to create a 4-bit adder with an output carry.

Contents  [hide] 1 Full-Adder in Verilog 1.1 Review 1.2 New Project 1.3 Functional Description of Full Adder 1.4 Logical Description of Full Adder 1.5 Gate-Level Description of Full Adder 1.6 Check Module for Syntax Errors 1.7 Generate a Test Module 1.7.1 Some explanations 1.8 Simulation 1.9 Better Simulation Output 2 A 4-Bit Adder 2.1 New Verilog Module 2.1.1 Explanations 2.2 Test Module

Full-Adder in Verilog