源自
http://www.asic-world.com/examples/verilog/d_ff.html
| D Flip-Flop | ||
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 | Asynchronous reset D- FF | |
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1 //----------------------------------------------------- 2 // Design Name : dff_async_reset 3 // File Name : dff_async_reset.v 4 // Function : D flip-flop async reset 5 // Coder : Deepak Kumar Tala 6 //----------------------------------------------------- 7 module dff_async_reset ( 8 data , // Data Input 9 clk , // Clock Input 10 reset , // Reset input 11 q // Q output 12 ); 13 //-----------Input Ports--------------- 14 input data, clk, reset ; 15 16 //-----------Output Ports--------------- 17 output q; 18 19 //------------Internal Variables-------- 20 reg q; 21 22 //-------------Code Starts Here--------- 23 always @ ( posedge clk or negedge reset) 24 if (~reset) begin 25 q <= 1'b0; 26 end else begin 27 q <= data; 28 end 29 30 endmodule //End Of Module dff_async_resetYou could download file dff_async_reset.v here | ||
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| Synchronous reset D- FF | |
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1 //----------------------------------------------------- 2 // Design Name : dff_sync_reset 3 // File Name : dff_sync_reset.v 4 // Function : D flip-flop sync reset 5 // Coder : Deepak Kumar Tala 6 //----------------------------------------------------- 7 module dff_sync_reset ( 8 data , // Data Input 9 clk , // Clock Input 10 reset , // Reset input 11 q // Q output 12 ); 13 //-----------Input Ports--------------- 14 input data, clk, reset ; 15 16 //-----------Output Ports--------------- 17 output q; 18 19 //------------Internal Variables-------- 20 reg q; 21 22 //-------------Code Starts Here--------- 23 always @ ( posedge clk) 24 if (~reset) begin 25 q <= 1'b0; 26 end else begin 27 q <= data; 28 end 29 30 endmodule //End Of Module dff_sync_reset |
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