設計一個具有Reset 功能的D


//DE2-70 Pin assignments
//SW[0]  PIN_N25 --> Din
//SW[1]  PIN_N26 --> Reset_n
//KEY[0]  PIN_G26 --> Clk
//LEDG[0] PIN_AE22 -->Q
//LEDG[1] PIN_AF22 -->Qbar


module  D_FF(Din , Reset_n , Clk, Q, Qbar);    // dataflow style
input Din ,Reset_n , Clk ;
output reg Q  ;
output Qbar  ;

always @(posedge Clk or negedge Reset_n)
    begin
if (~Reset_n)
   Q <= 1'b0;
else
   Q <= Din;
end         

  assign Qbar=~Q;  

endmodule

/*
9 `timescale 1ns/1ns
10 
11 module d_ff_rtl (
12   clk,
13   rst_n,
14   d_i,
15   q_o
16 );
17 
18 input  clk;
19 input  rst_n;
20 input  d_i;
21 output reg q_o;
22 
23 always@(posedge clk, negedge rst_n) begin
24   if (~rst_n)
25     q_o <= 1'b0;
26   else
27     q_o <= d_i;
28 end
29 
30 endmodule
*/