http://www.worlduc.com/blog2012.aspx?bid=16544240
//div50MHZ.v
module div50MHZ(clk_50MHZ,clk_1HZ);
input clk_50MHZ;
output clk_1HZ;
reg clk_1HZ;
reg cnt=24999999;
always@(posedge clk_50MHZ)
if(cnt==24999999)
begin
cnt<=0;
clk_1HZ<=~clk_1HZ;
end
else
cnt<=cnt+1'b1;
endmodule
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