8 bit PARALLEL DIVIDER

8 bit PARALLEL DIVIDER

module divider8(q,out,a,b);// main module for parallel 8-bit divider

  input [7:0]a;//dividend

  input [3:0]b;//divisor

  output [3:0]out;//reminder

  output [4:0]q;//quotient

  wire [3:0]r1,r2,r3,r4;

  stage s1(q[4],r1[3:0],{1'b1},a[7:4],b[3:0]);

  stage s2(q[3],r2[3:0],q[4],{r1[2:0],a[3]},b[3:0]);

  stage s3(q[2],r3[3:0],q[3],{r2[2:0],a[2]},b[3:0]);

  stage s4(q[1],r4[3:0],q[2],{r3[2:0],a[1]},b[3:0]);

  stage s5(q[0],out[3:0],q[1],{r4[2:0],a[0]},b[3:0]);

endmodule     

module stage(q,out,t,a,b); // submodule      

  input [3:0]a;

  input [3:0]b;

  input t;

  output [3:0]out;

  output q;

  wire [3:0]c;

  cas ca1(out[0],c[0],t,b[0],a[0],t);

  cas ca2(out[1],c[1],t,b[1],a[1],c[0]);

  cas ca3(out[2],c[2],t,b[2],a[2],c[1]);

  cas ca4(out[3],c[3],t,b[3],a[3],c[2]);

  not n1(q,out[3]);

endmodule

           

module cas(out,cout,t,divisor,rin,cin); //controlled add-subtract

  input t,divisor,rin,cin;

  output cout,out;

  wire x;

  xor x1(x,t,divisor);

  fadd f1(out,cout,x,rin,cin);

endmodule

module fadd(s,cout,a,b,c); //full adder submodule

  input a,b,c;

  output s,cout;

  wire w1,w2,w3;

  and a1(w1,a,b);

  and a2(w2,b,c);

  and a3(w3,c,a);

  xor x1(s,a,b,c);

  or o1(cout,w1,w2,w3);

endmodule