2 digit BCD Adder 00+00+0=00 ~99+99+1=199
module _2digit_BCDAdder(SW, LEDR, LEDG , CLOCK_27 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,,HEX4,HEX5,HEX6,HEX7 );
input [17:0] SW; // toggle switches
input [7:0] KEY; // Push bottom
input CLOCK_27; //Clock 27MHz , 50Mhz
output [17:0] LEDR; // red LEDS
output [8:0] LEDG; // green LEDs
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; //7-segment display
reg [3:0] a1,a0;
reg [3:0] b1,b0;
reg cin;
wire [3:0] S1,S0;
wire C4,C8;
wire [7:0] segout0; //HEX 0
wire [7:0] segout1; //HEX 1
wire [7:0] segout2; //HEX 2
assign LEDR[17:0]=SW[17:0];
always@(SW)
begin
a0=SW[3:0];
a1=SW[7:4];
b0=SW[11:8];
b1=SW[15:12];
cin=SW[17];
end
BCD_adder U0(a0,b0,cin,S0,C4);
BCD_adder U1(a1,b1,C4,S1,C8);
//Display BCD Sum to 7-segment Display
_7seg UUT0(.hex(S0),.seg(segout0));
_7seg UUT1(.hex(S1),.seg(segout1));
_7seg UUT2(.hex({3'b000,C8}),.seg(segout2));
assign HEX0=segout0[6:0];
assign HEX1=segout1[6:0];
assign HEX2=segout2[6:0];
assign HEX3=7'h7f; //Blank 7-segment
assign HEX4=7'h7f;
assign HEX5=7'h7f; //Blank 7-segment
assign HEX6=7'h7f;
assign HEX7=7'h7f; //set 1 => off LED
endmodule
module BCD_adder(a,b,cin,s,cout);
input [3:0]a,b;
input cin;
output [3:0]s;
output cout;
reg [3:0]s,a_tmp,b_tmp;
reg cout;
reg [4:0]z; //5bit Sum
always @ ( a or b )
begin
if (a>9)
a_tmp= 4'b1001; //若是>9 則為9
else
a_tmp=a;
if (b>9)
b_tmp = 4'b1001; //若是>9 則為9
else
b_tmp=b;
end
always@(a_tmp or b_tmp or cin)
begin
z=a_tmp+b_tmp+cin;
if (z>9)
{cout,s}=z+6;
else
{cout,s}=z;
end
endmodule
//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//-----------------------------------------
module _7seg(hex , seg);
input [3:0] hex;
output [7:0] seg;
reg [7:0] seg;
// segment encoding
// 0
// ---
// 5 | | 1
// --- <- 6
// 4 | | 2
// ---
// 3
always @(hex)
begin
case (hex)
// Dot point is always disable
4'b0001 : seg = 8'b11111001; //1 = F9H
4'b0010 : seg = 8'b10100100; //2 = A4H
4'b0011 : seg = 8'b10110000; //3 = B0H
4'b0100 : seg = 8'b10011001; //4 = 99H
4'b0101 : seg = 8'b10010010; //5 = 92H
4'b0110 : seg = 8'b10000010; //6 = 82H
4'b0111 : seg = 8'b11111000; //7 = F8H
4'b1000 : seg = 8'b10000000; //8 = 80H
4'b1001 : seg = 8'b10010000; //9 = 90H
4'b1010 : seg = 8'b10001000; //A = 88H
4'b1011 : seg = 8'b10000011; //b = 83H
4'b1100 : seg = 8'b11000110; //C = C6H
4'b1101 : seg = 8'b10100001; //d = A1H
4'b1110 : seg = 8'b10000110; //E = 86H
4'b1111 : seg = 8'b10001110; //F = 8EH
default : seg = 8'b11000000; //0 = C0H
endcase
end
endmodule
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