HDLBits/Sequential Logic/Finite State Machines/Fsm ps2data

 HDLBits/Sequential Logic/Finite State Machines/Fsm ps2data

See also: PS/2 packet parser.

Now that you have a state machine that will identify three-byte messages in a PS/2 byte stream, add a datapath that will also output the 24-bit (3 byte) message whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the second byte, etc.).

out_bytes needs to be valid whenever the done signal is asserted. You may output anything at other times (i.e., don't-care).

For example:

在接收完後完整的輸出後將接收的3個BYTE DATA。

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //
 
    parameter BYTE1 = 4'b0001;
    parameter BYTE2 = 4'b0010;
    parameter BYTE3 = 4'b0100;
    parameter DONE  = 4'b1000;
    reg [3:0] state, next_state;
    
    always @(posedge clk)begin
        if(reset)begin
            state <= BYTE1;
        end
        else begin
            state <= next_state;
        end
    end
    
    always @(*)begin
        next_state = 4'd0;
        case(state)
            BYTE1:next_state=in[3]?BYTE2:BYTE1;
            BYTE2:next_state=BYTE3;
            BYTE3:next_state=DONE;
            DONE:next_state=in[3]?BYTE2:BYTE1;
            default:next_state=BYTE1;
        endcase
    end

    // Output logic
    reg [7:0] db1,db2,db3;       //db=>data_byte
    assign done = (state == DONE);
    always @(posedge clk)begin
        if(reset)begin
            db1 <= 8'd0;
            db2 <= 8'd0;
            db3 <= 8'd0;
        end
        else begin
            case(next_state)
                BYTE2:db1 <= in;
                BYTE3:db2 <= in;
                DONE:db3 <= in;
            endcase
        end
    end
    assign out_bytes = {db1,db2,db3};
endmodule