alex9ufo 聰明人求知心切: HDLBits/Building Larger Circuits/Counter with period 1000（Exams/review2015 count1k）

2021年7月3日星期六

HDLBits/Building Larger Circuits/Counter with period 1000（Exams/review2015 count1k）

HDLBits/Building Larger Circuits/Counter with period 1000（Exams/review2015 count1k）

Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0.

module top_module (
input clk,
input reset,
output [9:0] q);
always@(posedge clk) begin
if (reset)
q=10'd0;
else if (q==10'd999)
q=10'd0;
else
q=q+1;
end
endmodule

alex9ufo 聰明人求知心切

2021年7月3日星期六

HDLBits/Building Larger Circuits/Counter with period 1000（Exams/review2015 count1k）

module top_module (
input clk,
input reset,
output [9:0] q);
always@(posedge clk) begin
if (reset)
q=10'd0;
else if (q==10'd999)
q=10'd0;
else
q=q+1;
end
endmodule

沒有留言:

張貼留言

Messaging API作為替代方案

2021年7月3日 星期六

HDLBits/Building Larger Circuits/Counter with period 1000（Exams/review2015 count1k）

module top_module ( input clk, input reset, output [9:0] q); always@(posedge clk) begin if (reset) q=10'd0; else if (q==10'd999) q=10'd0; else q=q+1; endendmodule

沒有留言:

張貼留言

Messaging API作為替代方案

2021年7月3日星期六

module top_module (
input clk,
input reset,
output [9:0] q);
always@(posedge clk) begin
if (reset)
q=10'd0;
else if (q==10'd999)
q=10'd0;
else
q=q+1;
end
endmodule