Verilog Course

Verilog Course

https://www.cis.upenn.edu/~milom/cis371-Spring13/lab/textbook-verilog-tutorial/VOL/main.htm

How to Take This Course

CHAPTER 1 - Introduction, Hierarchy, and Modelling Structures

This section provides background about the history of Verilog. It also introduces some of the basic contructs of Verilog models.

CHAPTER 2 - Syntax, Lexical Conventions, Data Types, and Memories

This section addresses the syntax and semantics of the core features of the language.

CHAPTER 3 - Expressions and Simulation Mechanics

This section covers the components of Verilog expressions and the order of execution in Verilog models.

CHAPTER 4 - Gate Level Modelling

This section covers gate level modelling constructs. It covers the semantics of Verilog primitives, port expressions, delays, strengths, and user-defined primitives.

CHAPTER 5 - Behavioral and Register Transfer Level Modelling

This section covers the remainder of the language basics: assignments of all kinds, control constructs, time and event controls, tasks and functions, and examples.

CHAPTER 6 - Advanced Features

Advanced features include all the details and less common features of the language. This includes cross-module references, quasi-continuous assigns, declared events, disable, and timing features, including timescales and specify blocks.

CHAPTER 7 - Coding Style

This section covers Verilog coding style. There are many different ways to write Verilog code, and some are better than others. It covers modelling clocks, state machines, pipelines, 0-delay code, and race conditions, as well as efficient coding techniques.

CHAPTER 8 - Debugging Verilog Models

This section discusses debugging techniques. It is simulator-independent as much as possible, as it covers broadly applicable debugging methods. These include setting breakpoints interactively, monitoring, using the CLI, using waveform viewers, and using $save.

CHAPTER 9 - The Programming Language Interface

This section is an introduction to the PLI. It covers what the PLI is used for, how user routines are connected to a Verilog model, passing information to and from the model and user routine, the TF routines, and the ACC routines. This section covers everything needed to write a PLI routine and link it into a simulator.