vhdl 4 bit adder

vhdl 4 bit adder

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library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_arith.all;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

entity adder_4bit is

     port(

         a : in STD_LOGIC_VECTOR(3 downto 0);

         b : in STD_LOGIC_VECTOR(3 downto 0);

         carry : out STD_LOGIC;

         sum : out STD_LOGIC_VECTOR(3 downto 0)

         );

end adder_4bit;

architecture adder_4bit_arc of adder_4bit is

 

signal Temp1 : std_logic_vector (4 downto 0);

begin 

    Temp1 <= ("0" &  a ) + b ; 

    sum <=Temp1 (3 downto 0);

    carry <= Temp1(4);

end adder_4bit_arc;