BCD計數器 0-99 顯示於7-segment

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned;
-- pin 86 selector de display 1
-- pin 87 selec2 display
-- Seg A pin 85, Seg B 84, Seg C 83, D 82, E 81, F 78, Seg g pin 77, H 76
entity cnt_99 is
    port(
        CLK : in std_logic; -- se le asigna el pin   12
        --clk1hz : out std_logic ;-- se le asigna el pin 51
        datos : out std_logic_vector (6 downto 0);
        unidades : out std_logic;
        decenas: out std_logic
    );
end entity;

architecture BH_Examen2Parcial of cnt_99 is
    signal freq1 : integer range 0 to 5000 := 0;
    signal freqDec : integer range 0 to 24999999 := 0;
    signal freq100 : integer range 0 to 249999999 := 0;
 
    signal tmp1 : std_logic := '0';
    signal tmp100 : std_logic := '0';
    signal tmpDec : std_logic := '0';
    signal counterUnidades : integer range 0 to 10 := 0;
    signal counterDecenas : integer range 0 to 10 := 0;
    signal segDecenas : std_logic_vector(6 downto 0);
    signal segUnidades : std_logic_vector(6 downto 0);

 begin
    process(CLK) is
    begin
        if(CLK'event and CLK = '1') then
            if(freq1 >= 5000) then
                freq1 <= 0;
                tmp1 <= not tmp1;
            else
                freq1 <= freq1 + 1;
            --    tmp1 <= tmp1;
            end if;

            if(freqDec >= 24999999) then
                freqDec <= 0;
                tmpDec <= not tmpDec;
            else
                freqDec <= freqDec + 1;
               -- tmpDec <= tmpDec;
            end if;
         end if;
   end process;


 process(tmp1) is
    begin
        if(tmp1 = '1') then
            unidades <= '0';
            decenas <= '1';
            datos <= segDecenas;
        else
            datos <= SegUnidades;
            decenas <= '0';
            unidades <= '1';
        end if;
    end process;


--ParaContarUnidades:
---------------------------------------------------
---a,b,c,d,e,f,g,dp---  0 : on  1: off
---------------------------------------------------

ParaContarDecenas:
  process(tmpDec) is
    begin
        if (tmpDec = '1') then
            if(counterDecenas = 0) then
                segDecenas <= "0000001";
            elsif (counterDecenas = 1 ) then
                segDecenas <= "1001111";
            elsif (counterDecenas = 2 ) then
                segDecenas <= "0010010";
            elsif (counterDecenas = 3 ) then
                segDecenas <= "0000110";
            elsif (counterDecenas = 4 ) then
                segDecenas <= "1001100";
            elsif (counterDecenas = 5 ) then
                segDecenas <= "0100100";
            elsif (counterDecenas = 6 ) then
                segDecenas <= "1100000";
            elsif (counterDecenas = 7 ) then
                segDecenas <= "0001111";
            elsif (counterDecenas = 8 ) then
                segDecenas <= "0000000";
            elsif (counterDecenas = 9) then
                segDecenas <= "0001100";
            else
                segDecenas <= "1111111";
            end if;
         
---------------------------------------------------------
-- ParaContarUnidades:process(tmp100) is
---------------------------------------------------------    
           if(counterUnidades = 0) then
               segUnidades <= "0000001";
           elsif (counterUnidades = 1 ) then
               segUnidades <= "1001111";
           elsif (counterUnidades = 2 ) then
               segUnidades <= "0010010";
           elsif (counterUnidades = 3 ) then
               segUnidades <= "0000110";
           elsif (counterUnidades = 4 ) then
               segUnidades <= "1001100";
           elsif (counterUnidades = 5 ) then
               segUnidades <= "0100100";
           elsif (counterUnidades = 6 ) then
               segUnidades <= "1100000";
           elsif (counterUnidades = 7 ) then
              segUnidades <= "0001111";
           elsif (counterUnidades = 8 ) then
               segUnidades <= "0000000";
          elsif (counterUnidades = 9) then
               segUnidades <= "0001100";
          else
               segUnidades <= "1111111";
          end if;


           
            if(counterDecenas >= 9) then
                counterDecenas <= 0;
if(counterUnidades >= 9) then
counterUnidades <= 0;            
else
counterUnidades <= counterUnidades + 1;
end if;
            else
                counterDecenas <= counterDecenas + 1;
            end if;


        end if;
     
    end process;
 
end architecture;

七段LED顯示解碼器

----
--使用VHDL設計一個七段LED顯示解碼器
--說明：利用VHDL將電路圖以文字敘述方式寫出
--binary x[3..0] ==> y[6..0]=a.b.c.d.e.f.g
--common Anode
--
--------------------------------------------------------------
library ieee;    --宣告要使用的零件庫
use ieee.std_logic_1164.all;
entity bin_7seg is  --宣告元件外部I/O接角的規格

port(
   
     x:in std_logic_vector(3 downto 0); --接腳名稱：輸出入狀態資料形態
     y:out std_logic_vector(6 downto 0) ---y[6]=a y[5]=b....y[0]=g
   
     );

end bin_7seg;

architecture arch of bin_7seg is --描述元件內部的功能

begin

with x select

y<="0000001"when"0000",  --電路內部描述 command

   "1001111"when"0001",  ---a,b,c,d,e,f,g

   "0010010"when"0010",

   "0000110"when"0011",

   "1001100"when"0100",

   "0100100"when"0101",

   "0100000"when"0110",

   "0001111"when"0111",

   "0000000"when"1000",

   "0000100"when"1001",

   "0001000"when"1010",

   "1100000"when"1011",

   "0110001"when"1100",

   "1000010"when"1101",

   "0110000"when"1110",

   "0111000"when"1111",

   "1111111"when others;

end arch ;

BCD計數器 0-9 顯示於7-segment

輸入 :　clock :=48Mhz
              reset := push button
輸出：1 digit 7-segment


48Mhz -> 1Hz ->0..9 BCD conuter -> 7segment

----
--VHDL code for BCD to 7-segment display converter
----
--------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cnt_9 is
port (
      Clk : in std_logic;
      Rst : in std_logic;
      segment7 : out std_logic_vector(6 downto 0)  -- 7 bit decoded output.
    );
end cnt_9;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of cnt_9 is

   signal temp: std_logic_vector(0 to 3);
   signal Fre_1hz : std_logic ; --1Hz 基頻
   signal Pulse : std_logic ; --按鍵防彈跳頻率
 
begin

Clk_generator:  process(Clk)
variable Delay : std_logic_vector(24 downto 0); begin
if rising_edge(Clk) then
if Delay=24000000 then Delay := "0000000000000000000000000" ; --–-將輸入頻率除頻成 1Hz
Fre_1hz <= not Fre_1hz ; else Delay := Delay+1 ; end if ;
Pulse <= Delay(14); ---產生防彈跳頻率
end if ;
 end process Clk_generator ;

 
 BCD_CNT: process(Fre_1hz,Rst)
  begin
      if Rst='1' then
         temp <= "0000";
      elsif(rising_edge(Fre_1hz)) then
        if temp="1001" then
      temp<="0000";
   else
      temp <= temp + 1;
   end if;
      end if;
 
   end process;
------------------------------------------------------  
bcd_7seg: process (clk,temp)
BEGIN
if (Clk'event and Clk='1') then
case  temp is
when "0000"=> segment7 <="0000001";  -- '0'
when "0001"=> segment7 <="1001111";  -- '1'
when "0010"=> segment7 <="0010010";  -- '2'
when "0011"=> segment7 <="0000110";  -- '3'
when "0100"=> segment7 <="1001100";  -- '4'
when "0101"=> segment7 <="0100100";  -- '5'
when "0110"=> segment7 <="0100000";  -- '6'
when "0111"=> segment7 <="0001111";  -- '7'
when "1000"=> segment7 <="0000000";  -- '8'
when "1001"=> segment7 <="0000100";  -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end if;
end process;


end Behavioral;

VHDL Generating the Clock Source (divided 32 5 bits)

VHDL   Generating the Clock Source


---
--
--Outputs
--LED1 <= CLK1; simply routes the source clock (130Hz) to LED 1.
--LED2 <= CLK_DIV(4); routes bit 4 of the CLK_DIV register to LED 2.
--        This is input clock pulse divided by 32.
--
---

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock_divider_top is
    Port ( CLK1    : in  STD_LOGIC;
           Clear   : in  STD_LOGIC;
           LED1    : out STD_LOGIC;
           LED2    : out STD_LOGIC);
end clock_divider_top;

architecture Behavioral of clock_divider_top is
signal CLK_DIV : std_logic_vector (4 downto 0);  
-- routes bit 4 of the CLK_DIV register to LED 2.
-- LED2 <= CLK_DIV(4);   ----div 32
-- signal CLK_DIV : std_logic_vector (9 downto 0);  
-- LED2 <= CLK_DIV(9);   ----div 1024

begin
    -- clock divider
    -- behavioral description of the counter
   process(CLK1, Clear) begin
     if Clear = '0' then
       CLK_DIV <= "00000";
     elsif (CLK1'Event and CLK1 = '1') then
            CLK_DIV <= CLK_DIV + 1 ;
     end if;
   end process;
 
   LED1 <= CLK_DIV(0);
   LED2 <= CLK_DIV(4);
 
end Behavioral ;  

vhdl 4 bit adder

vhdl 4 bit adder

  PPT  下載點

  VHDL file 下載點

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_arith.all;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

entity adder_4bit is

     port(

         a : in STD_LOGIC_VECTOR(3 downto 0);

         b : in STD_LOGIC_VECTOR(3 downto 0);

         carry : out STD_LOGIC;

         sum : out STD_LOGIC_VECTOR(3 downto 0)

         );

end adder_4bit;

architecture adder_4bit_arc of adder_4bit is

 

signal Temp1 : std_logic_vector (4 downto 0);

begin 

    Temp1 <= ("0" &  a ) + b ; 

    sum <=Temp1 (3 downto 0);

    carry <= Temp1(4);

end adder_4bit_arc;            

學習使用VHDL 建立電路及燒錄流程。

VHDL數位電路設計 入門範例－HelloVHDL.qpf 
 
                                            下載點

  學習目標： 

      1.   學習使用VHDL 建立電路及燒錄流程。 

      2.   瞭解電路程式基本結構(library + entity + architecture) 

      3.   瞭解 「訊號指定」敘述  <= 

      4.   瞭解「註解」用法 

      5.   瞭解「識別字」名稱規則 

  功能說明： 

      電路為一個2 輸入端的XOR 閘，輸入接到兩只指撥開關，輸出連接一只LED 。



  修改
 泰山高中 電機科       授課教師：鄭聰賢  

手機與Arduino 互動入門 (2/3) 勤益科大 上課 講義----更新 5/2

手機與Arduino 互動入門 (2/3) 勤益科大 上課 講義

----更新日期  5/2

新增  步進馬達 控制

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 步進馬達 控制程式1

 步進馬達 控制程式2

 步進馬達 控制程式3

 步進馬達 控制程式4

光華高工 數位電路 期末數位電路設計 題庫

光華高工 數位電路 期末數位電路 設計 題庫

麻煩告知 資訊三仁 同學 下載位置

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