Verilog HDL: Procedural Assignments

源自

 http://asic-soc.blogspot.tw/2012/03/verilog-hdl-procedural-assignments.html

Verilog HDL: Procedural Assignments

Procedural  Assignments :-

This  update  values  of  reg, integer,real or time variables.  The  value  placed  on  a  variable  will remain unchanged  until another  procedural   assignment  updates  the  variable  with  a  different  value.

The  lefthand  side  of  a  procedural  assignment  <lvalue>   can  be  one  of  the  following :

      reg, integer,real or time  register  variable  or  a memory  element

      bit  select  of  those  variables (eg : addr[0])

      part  select  of  those  variables (eg :  addr[31:16])

      concatenation  of  any  of  the  above

There  are  two  types  of  procedural  assignment  statements :

1)       Blocking

2)      Nonblocking

Blocking  Assignment :-

Are  executed  in  the  order  they  are  specified   in  a  sequential  block.  It  will  not  block  execution  of  statements  that  follow  in  a  parallel  block.

Eg :-         reg  x,y,z;

                 reg  [15:0]   reg_a,reg_b;

                  integer  count;

                  initial         //all  behavioural   statements  must  be  inside  an  initial  or  always  block

                  begin

                              X=0;y=1;z=1;       //scalar    assignments

                               Count =0;          //assignment  to  integer  variables

                                Reg_a = 16’bo;     //initialize  vectors

                                Reg_b =reg_a;

                                 #15   reg_a[2] = 1’b1;    //bit  select  assignment  with  delay

                                 #10   reg_b[15:13] = {x,y,z}     //assign  result  of  concatenation  to part  select of  a  

                                                                                      // vector

                                 Count =count+1;

                                  end

Nonblocking  Assignment :-

Allows  scheduling  of  assignments  without  blocking  execution   of  the  statements  that  follows  in  a  sequential  block.  A   <=  operator  is  used  to  specify  nonblocking  assignments.

Eg :-

                 reg  x,y,z;

                 reg  [15:0]   reg_a,reg_b;

                  integer  count;

                  initial         //all  behavioural   statements  must  be  inside  an  initial  or  always  block

                  begin

                              X=0;y=1;z=1;       //scalar    assignments

                              Count =0;          //assignment  to  integer  variables

                              Reg_a = 16’bo;     //initialize  vectors

                              Reg_b =reg_a;

                              Reg_a[2] <=  #15  1’b1;

                              Reg_b[15:13] <=  #10 {x,y,z};

                               Count =count+1;

                          End

v  The simulator schedules  a   nonblocking  assignment  statements  to  execute  and  continues  to  the  next  statement  in  the  block  without  waiting  for  the  nonblocking  statement  to  complete  execution.

v  typical   applications :

o   pipeline  modeling

o   modeling  of  several  mutually  exclusive  data  transfer