源自於http://ghsi.de/CRC/
Online CRC Calculation
A typical hardware implementation (LFSR - Linear Feedback Shift Register) is shown here:
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Dr.-Ing. K. Gorontzi, 2005 | |||||||||||||||||||
The input bits are shifted into the very left XOR gate. The MSB is shifted in first.
Each flipflop represents a single CRC output bit. The leftmost flipflop is the MSB of the CRC. This implementation doesn't need to augment the serial input message with zeros.
Note that in our case the flipflops are cleared to zeros at the beginning of each CRC calculation.
A simple VERILOG implementation of the above polynom is shown here. You can directly copy the source snippet to your code (distributed under LGPL):
// ========================================================================== // CRC Generation Unit - Linear Feedback Shift Register implementation // (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL // ========================================================================== module CRC_Unit(BITVAL, BITSTRB, CLEAR, CRC); input BITVAL; // Next input bit input BITSTRB; // Current bit valid (Clock) input CLEAR; // Init CRC value output [15:0] CRC; // Current output CRC value reg [15:0] CRC; // We need output registers wire inv; assign inv = BITVAL ^ CRC[15]; // XOR required? always @(posedge BITSTRB or posedge CLEAR) begin if (CLEAR) begin CRC = 0; // Init before calculation end else begin CRC[15] = CRC[14]; CRC[14] = CRC[13]; CRC[13] = CRC[12]; CRC[12] = CRC[11] ^ inv; CRC[11] = CRC[10]; CRC[10] = CRC[9]; CRC[9] = CRC[8]; CRC[8] = CRC[7]; CRC[7] = CRC[6]; CRC[6] = CRC[5]; CRC[5] = CRC[4] ^ inv; CRC[4] = CRC[3]; CRC[3] = CRC[2]; CRC[2] = CRC[1]; CRC[1] = CRC[0]; CRC[0] = inv; end end endmodule
源自於
http://www.asic-world.com/examples/verilog/serial_crc.html
| Serial CRC |
Below code is 16-bit CRC-CCITT implementation, with following features
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1 //----------------------------------------------------- 2 // Design Name : serial_crc_ccitt 3 // File Name : serial_crc.v 4 // Function : CCITT Serial CRC 5 // Coder : Deepak Kumar Tala 6 //----------------------------------------------------- 7 module serial_crc_ccitt ( 8 clk , 9 reset , 10 enable , 11 init , 12 data_in , 13 crc_out 14 ); 15 //-----------Input Ports--------------- 16 input clk ; 17 input reset ; 18 input enable ; 19 input init ; 20 input data_in ; 21 //-----------Output Ports--------------- 22 output [15:0] crc_out; 23 //------------Internal Variables-------- 24 reg [15:0] lfsr; 25 //-------------Code Start----------------- 26 assign crc_out = lfsr; 27 // Logic to CRC Calculation 28 always @ (posedge clk) 29 if (reset) begin 30 lfsr <= 16'hFFFF; 31 end else if (enable) begin 32 if (init) begin 33 lfsr <= 16'hFFFF; 34 end else begin 35 lfsr[0] <= data_in ^ lfsr[15]; 36 lfsr[1] <= lfsr[0]; 37 lfsr[2] <= lfsr[1]; 38 lfsr[3] <= lfsr[2]; 39 lfsr[4] <= lfsr[3]; 40 lfsr[5] <= lfsr[4] ^ data_in ^ lfsr[15]; 41 lfsr[6] <= lfsr[5]; 42 lfsr[7] <= lfsr[6]; 43 lfsr[8] <= lfsr[7]; 44 lfsr[9] <= lfsr[8]; 45 lfsr[10] <= lfsr[9]; 46 lfsr[11] <= lfsr[10]; 47 lfsr[12] <= lfsr[11] ^ data_in ^ lfsr[15]; 48 lfsr[13] <= lfsr[12]; 49 lfsr[14] <= lfsr[13]; 50 lfsr[15] <= lfsr[14]; 51 end 52 end 53 54 endmoduleYou could download file serial_crc.v here |
