P3-15

module tribuff(dbus,enab,inputval);

    inout [3:0]dbus;

    input enab;

    input [3:0]inputval;

    assign dbus = enab ? inputval : 4'bZ;

endmodule

以De2-70 實現 P3-15 功能

modelsim simulation


`timescale 1us/1us

module testbench();


// Inputs
    reg enab;
    reg inputval;

// Outputs
    wire dbus;


// Instantiate the UUT
// tribuff(dbus,enab,inputval);;

    tribuff tribuffer(
        .dbus(dbus), 
        .enab(enab), 
        .inputval(inputval)
        );

initial
 $monitor ($time, "enab=%b,inputval=%b,dbus=%b", enab,inputval,dbus);

initial //Initialize input signals
 begin
    inputval = 4'b0;   //0-50 
    enab = 0;
 end

initial 
 begin
   #50  enab=0 ; inputval=4'b1111;     //50-100  
   #50  enab=1 ; inputval=4'b1111;     //100-150
   #50  enab=0 ; inputval=4'b1010;     //150-200  
   #50  enab=1 ; inputval=4'b1010;     //200-250 
   #50  enab=0 ; inputval=4'b0101;     //250-300  
   #50  enab=1 ; inputval=4'b0101;     //300-350 
 end

initial #400 $finish;        //Complete simulation after 250us
  
endmodule

電路圖-----另一方法2 TINA

電路圖-----另一方法2

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Eagle教學----電路圖 (另一方法)

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This Verilog tutorial was started a long time ago. Every time I update my web page, I make sure I add something new in the Verilog tutorial section. If you have been a frequent visitor, you should have noticed how these tutorial pages have improved. I hope some day this Verilog tutorial becomes a reference for all the engineers out there. Of course, new learners will always find this tutorial useful. All the examples have been simulated using Icarus Verilog simulator. Currently this website is getting more than 1 million hits every month. A special thanks to Paolo Franchetti for fixing grammar and spelling mistakes in Verilog tutorial. Important :This tutorial is best seen using firefox web browser and may not look well on Internet Explorer.   Introduction   Verilog In One Day   History Of Verilog   Design And Tool Flow   My first program in Verilog   Verilog HDL Syntax And Semantics   Gate Level Modeling   User Defined Primitives   Verilog Operators   Verilog Behavioral Modeling   Procedural Timing Control   Task And Functions   System Task and Function   Art of Writing TestBenches   Modeling Memories And FSM   Parameterized Modules   Verilog Synthesis Tutorial   Verilog PLI Tutorial   What's new in Verilog 2001   Assertions In Verilog   Compiler Directives   Verilog Quick Reference