RS Flip Flop with Enable in Verilog

RS Flip Flop with Enable in Verilog

//===========================================
// RS Flip Flop with Enable control
//===========================================
module RS_FF( en, S, R, Q, Qbar);
  input en, S, R;
  output Q, Qbar;
  wire Senbar,Renbar;
  
  assign Senbar = ~(en & S);
  assign Renbar = ~(en & R);
  
  RS_latch L1(Senbar, Renbar, Q, Qbar);
endmodule


module RS_latch(Sbar, Rbar, Q, Qbar);
  input Sbar, Rbar;
  output Q, Qbar;
  
  assign Q   = ~(Sbar & Qbar);
  assign Qbar= ~(Rbar & Q);

endmodule

// 時間單位 1ns, 時間精確度10 ps
`timescale 10ns/10ps 
module TB;
/*
module RS_FF(input en, S, R, output Q, Qbar);
  input en, S, R;
  output Q, Qbar;
*/
reg S, en, R;
wire Q, Qbar;

RS_FF  UUT(en, S, R, Q, Qbar);


always #50 begin
  en = 1;
  #50;
  S = 1; R = 0;
  #50;
  S = 0; R = 0;
  #50;
  S = 0; R = 1;
  #50
  en = 0;
  #50;
  S = 1; R = 0;
  #50;
  S = 0; R = 0;
  #50;
  S = 0; R = 1;
end

initial #1000 $finish;


endmodule

RS Latch in Verilog

RS Latch in Verilog 

//===============

//Gate level
//===============

module RS_Latch(Sbar, Rbar, Q, Qbar);
input Sbar, Rbar;
output Q, Qbar;

  nand LS(Q, Sbar, Qbar);
  nand LR(Qbar, Rbar, Q);
endmodule

//===============

//Data flow level
//===============
module RS_Latch(Sbar, Rbar, Q, Qbar);
input Sbar, Rbar;
output Q, Qbar;

  assign Q   = ~(Sbar & Qbar);
  assign Qbar= ~(Rbar & Q);
endmodule

// 時間單位 1ns, 時間精確度10 ps
`timescale 10ns/10ps
module TB;
reg Sbar, Rbar;
wire Q, Qbar;

RS_Latch UUT(Sbar, Rbar, Q, Qbar);

always #50 begin
  Sbar = 0; Rbar = 1;
  #50;
  Sbar = 1; Rbar = 1;
  #50;
  Sbar = 1; Rbar = 0;
  #50;
end

initial #500 $finish;

endmodule

Dataflow level D flip flop in Verilog

Dataflow level D flip flop in Verilog

//========================================
// Dataflow level D flip flop in Verilog
//========================================
`timescale 10ns/10ps 
module D_FF(D,CLK,Q,Qbar);
input D,CLK;
output Q,Qbar;

wire d1,d2,d3,d4,d5,d6,d7,d8;

assign d1= ~(D & d3);
assign d2= ~(d1 & d3);
assign d3= ~ CLK;

assign d4= ~(d8 & d1);
assign d8= ~(d2 & d4);

assign d5 = ~ d3;

assign d6= ~(d4 & d5);
assign d7= ~(d6 & d5);

assign Q= ~(d6 & Qbar);
assign Qbar= ~(Q & d7);

endmodule

//==========================================

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps 

module TB;

/*

module D_FF(D,CLK,Q,Qbar);

input D,CLK;

output Q,Qbar;

*/

reg D,CLK= 1'b10;   //  暫存器資料初值為‘0’

wire Q,Qbar;

integer i;

D_FF  UUT (D,CLK,Q,Qbar);

initial begin

    for (i=0; i<5; i=i+1) begin

          D = i;

         #35;

    end

    #25

     $stop;

end

always

begin

#25

     CLK=~CLK;

end 

endmodule

Verilog code for Rising Edge D Flip Flop

Verilog code for Rising Edge D Flip Flop:

源自於 https://www.fpga4student.com/2017/02/verilog-code-for-d-flip-flop.html

// FPGA projects using Verilog/ VHDL 
// fpga4student.com
// Verilog code for D Flip FLop
// Verilog code for rising edge D flip flop 
module RisingEdge_DFlipFlop(D,clk,Q);
input D; // Data input 
input clk; // clock input 
output Q; // output Q 
always @(posedge clk) 
begin
 Q <= D; 
end 
endmodule 

Verilog code for Rising Edge D Flip-Flop with Synchronous Reset:

// FPGA projects using Verilog/ VHDL 
// fpga4student.com
// Verilog code for D Flip FLop
// Verilog code for Rising edge D flip flop with Synchronous Reset input 
module RisingEdge_DFlipFlop_SyncReset(D,clk,sync_reset,Q);
input D; // Data input 
input clk; // clock input 
input sync_reset; // synchronous reset 
output reg Q; // output Q 
always @(posedge clk) 
begin
 if(sync_reset==1'b1)
  Q <= 1'b0; 
 else 
  Q <= D; 
end 
endmodule 

Verilog code for Rising Edge D Flip-Flop with Asynchronous Reset High Level:

// FPGA projects using Verilog/ VHDL 
// fpga4student.com
// Verilog code for D Flip FLop
// Verilog code for Rising edge D flip flop with Asynchronous Reset high
module RisingEdge_DFlipFlop_AsyncResetHigh(D,clk,async_reset,Q);
input D; // Data input 
input clk; // clock input 
input async_reset; // asynchronous reset high level
output reg Q; // output Q 
always @(posedge clk or posedge async_reset) 
begin
 if(async_reset==1'b1)
  Q <= 1'b0; 
 else 
  Q <= D; 
end 
endmodule 

Verilog code for Rising Edge D Flip-Flop with Asynchronous Reset Low Level:

// FPGA projects using Verilog/ VHDL 
// fpga4student.com
// Verilog code for D Flip FLop
// Verilog code for Rising edge D flip flop with Asynchronous Reset Low 
module RisingEdge_DFlipFlop_AsyncResetLow(D,clk,async_reset,Q);
input D; // Data input 
input clk; // clock input 
input async_reset; // asynchronous reset low level 
output reg Q; // output Q 
always @(posedge clk or negedge async_reset) 
begin
 if(async_reset==1'b0)
  Q <= 1'b0; 
 else 
  Q <= D; 
end 
endmodule 

Verilog code for Falling Edge D Flip Flop:

// FPGA projects using Verilog/ VHDL 
// fpga4student.com
// Verilog code for D Flip FLop
// Verilog code for falling edge D flip flop 
module FallingEdge_DFlipFlop(D,clk,Q);
input D; // Data input 
input clk; // clock input 
output reg Q; // output Q 
always @(negedge clk) 
begin
 Q <= D; 
end 
endmodule 

Verilog code for Falling Edge D Flip-Flop with Synchronous Reset:

// FPGA projects using Verilog/ VHDL 
// fpga4student.com
// Verilog code for D Flip FLop
// Verilog code for Falling edge D flip flop with Synchronous Reset input 
module FallingEdge_DFlipFlop_SyncReset(D,clk,sync_reset,Q);
input D; // Data input 
input clk; // clock input 
input sync_reset; // synchronous reset 
output reg Q; // output Q 
always @(negedge clk) 
begin
 if(sync_reset==1'b1)
  Q <= 1'b0; 
 else 
  Q <= D; 
end 
endmodule 

Verilog code for Falling Edge D Flip-Flop with Asynchronous Reset High Level:

// FPGA projects using Verilog/ VHDL 
// fpga4student.com
// Verilog code for D Flip FLop
// Verilog code for Falling edge D flip flop with Asynchronous Reset high
module FallingEdge_DFlipFlop_AsyncResetHigh(D,clk,async_reset,Q);
input D; // Data input 
input clk; // clock input 
input async_reset; // asynchronous reset high level 
output reg Q; // output Q 
always @(negedge clk or posedge async_reset) 
begin
 if(async_reset==1'b1)
  Q <= 1'b0; 
 else 
  Q <= D; 
end 
endmodule 

Verilog code for Falling Edge D Flip-Flop with Asynchronous Reset Low Level:

// FPGA projects using Verilog/ VHDL 
// fpga4student.com
// Verilog code for D Flip FLop
// Verilog code for Falling edge D flip flop with Asynchronous Reset low
module FallingEdge_DFlipFlop_AsyncResetLow(D,clk,async_reset,Q);
input D; // Data input 
input clk; // clock input 
input async_reset; // asynchronous reset low level 
output reg Q; // output Q 
always @(negedge clk or negedge async_reset) 
begin
 if(async_reset==1'b0)
  Q <= 1'b0; 
 else 
  Q <= D; 
end 
endmodule 

Verilog Testbench code to simulate and verify D Flip-Flop:

`timescale 1ns/1ps;
// FPGA projects using Verilog/ VHDL 
// fpga4student.com
// Verilog code for D Flip FLop
// Testbench Verilog code for verification
module tb_DFF();
reg D;
reg clk;
reg reset;
wire Q;

RisingEdge_DFlipFlop_SyncReset dut(D,clk,reset,Q);

initial begin
  clk=0;
     forever #10 clk = ~clk;  
end 
initial begin 
 reset=1;
 D <= 0;
 #100;
 reset=0;
 D <= 1;
 #100;
 D <= 0;
 #100;
 D <= 1;
end 
endmodule 

Dataflow level Full Subtractor in Verilog

Dataflow level Full Subtractor in Verilog

//=============================================

// Dataflow level Full Subtractor in Verilog

//=============================================

`timescale 10ns/10ps 

module Full_subtractor(A,B,Bin,D,Bout);

input A,B,Bin;

output D,Bout;

assign D= A^B^Bin;

assign Bout=(~A&B) | (~A&Bin) | (B&Bin);

endmodule

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps 

module TB;

/*

module Full_subtractor(A,B,Bin,D,Bout);

input A,B,Bin;

output D,Bout;

*/

reg A,B,Bin= 1'b0;   //  暫存器資料初值為‘0’

wire D,Bout;

integer i;

Full_subtractor UUT(A,B,Bin,D,Bout);

initial begin

    for (i=0; i<9; i=i+1) begin

         {A,B,Bin} = i;

         #20;

    end

    #20

     $stop;

end

endmodule

Dataflow 3 bits Majority in Verilog

Dataflow 3 bits Majority in Verilog

//========================
//Dataflow 3 bits Majority in Verilog
//========================
`timescale 10ns/10ps 
module major_3bit(I,Maj);
input [2:0]I;
output Maj;

assign Maj= (I[1] & I[0]) | ( I[2] & (I[1] | I[0]) ) ;

endmodule

//===============================

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps 

module TB;

/*

module major_3bit(I,Maj);

input [2:0]I;

output Maj;

*/

reg [2:0]I= 3'b000;   //  暫存器資料初值為‘000’

wire Maj;

integer i;

major_3bit UUT(I,Maj);

initial begin

    for (i=0; i<9; i=i+1) begin

         {I} = i;

         #20;

    end

    #20

     $stop;

end

endmodule

1x4 DeMux with bitwise operator in Verilog

1x4 DeMux with bitwise operator in Verilog

//========================
//Dataflow demux 1x4
//========================
`timescale 10ns/10ps
module Demux_1x4(I,S,Y);
input I;
input [1:0]S;
output [3:0]Y;

assign Y[0]= I & (~S[1]) & (~S[0]) ;
assign Y[1]= I & (~S[1]) & ( S[0]) ;
assign Y[2]= I & ( S[1]) & (~S[0]) ;
assign Y[3]= I & ( S[1]) & ( S[0]) ;

endmodule

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps 

module TB;

/*

module Demux_1x4(I,S,Y);

input I;

input [1:0]S;

output [3:0]Y;

*/

reg [1:0]S= 2'b00;   //  暫存器資料初值為‘00’

reg I=1'b0;

wire [3:0]Y;

integer i;

Demux_1x4 UUT (I,S,Y);

initial begin

    for (i=0; i<9; i=i+1) begin

         {I,S} = i;

         #20;

    end

    #20

     $stop;

end

endmodule