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2020年5月5日星期二

以Verilog 設計一個數位電路 (6)---3x8 decoder

以Verilog 設計一個數位電路 (6)---3x8 decoder

module block1(
a,
b
);
input [2:0] a;
output [7:0] b;

wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;

assign SYNTHESIZED_WIRE_14 = ~a[0];
assign SYNTHESIZED_WIRE_13 = ~a[1];
assign SYNTHESIZED_WIRE_12 = ~a[2];

assign b[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
assign b[1] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & a[0];
assign b[2] = SYNTHESIZED_WIRE_12 & a[1] & SYNTHESIZED_WIRE_14;
assign b[3] = SYNTHESIZED_WIRE_12 & a[1] & a[0];
assign b[4] = a[2] & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
assign b[5] = a[2] & SYNTHESIZED_WIRE_13 & a[0];
assign b[6] = a[2] & a[1] & SYNTHESIZED_WIRE_14;
assign b[7] = a[2] & a[1] & a[0];

endmodule

//==============================

`timescale 1 ns/1 ns

module EX_106 (a, b);

input [2:0] a;

output [7:0] b;

wire [7:0] b;

assign b[0] = ( a==3'b000 ) ? 1'b1 : 1'b0;

assign b[1] = ( a==3'b001 ) ? 1'b1 : 1'b0;

assign b[2] = ( a==3'b010 ) ? 1'b1 : 1'b0;

assign b[3] = ( a==3'b011 ) ? 1'b1 : 1'b0;

assign b[4] = ( a==3'b100 ) ? 1'b1 : 1'b0;

assign b[5] = ( a==3'b101 ) ? 1'b1 : 1'b0;

assign b[6] = ( a==3'b110 ) ? 1'b1 : 1'b0;

assign b[7] = ( a==3'b111 ) ? 1'b1 : 1'b0;

endmodule

//==============================

`timescale 100 ns/1 ns

module testbench;

reg [2:0] a;

wire[7:0] b;

integer i;

EX_106 UUT(

.a(a),

.b(b) );

initial

begin

for (i=0;i<=7;i=i+1) begin

a=i;

#20;

end

#20;

$stop;

end

endmodule

以Verilog 設計一個數位電路 (5)---Nested MUX

以Verilog 設計一個數位電路 (5)---Nested MUX

//================================
`timescale 1 ns/1 ns

module EX_105 (a, b, c, d, e, f, sel1, sel2, sel3);
input [3:0] a, b, d, e;
input sel1, sel2, sel3;

output [3:0] c, f;
wire [3:0] c, f;

assign c = ( sel1 ) ? a :
( sel2 ) ? b :
( sel3 ) ? d : e;

assign f = ( sel1 ) ? ((sel2) ? a : b) :
((sel3) ? d : e) ;

endmodule

//================================

`timescale 100 ns/1 ns

module testbench;
reg [3:0] a, b, d, e;
reg sel1, sel2, sel3;
wire [3:0] c, f;

EX_105 UUT(
.a(a),
.b(b),
.d(d),
.e(e),
.sel1(sel1),
.sel2(sel2),
.sel3(sel3),
.c(c),
.f(f) );
initial
begin
a = 4'b1010; // Time = 0
b = 4'b1011;
d = 4'b1101;
e = 4'b1110;
sel1 = 1'b0; sel2 = 1'b0; sel3 = 1'b0;
#50; // Time = 50
sel1 = 1'b0; sel2 = 1'b0; sel3 = 1'b1;
#50; // Time = 100
sel1 = 1'b0; sel2 = 1'b1; sel3 = 1'b0;
#50; // Time = 150
sel1 = 1'b0; sel2 = 1'b1; sel3 = 1'b1;
#50; // Time = 200
sel1 = 1'b1; sel2 = 1'b0; sel3 = 1'b0;
#50; // Time = 250
sel1 = 1'b1; sel2 = 1'b0; sel3 = 1'b1;
#50; // Time = 300
sel1 = 1'b1; sel2 = 1'b1; sel3 = 1'b0;
#50; // Time = 300
sel1 = 1'b1; sel2 = 1'b1; sel3 = 1'b1;
#50;
$stop;
end
endmodule

2020年5月3日星期日

以Verilog 設計一個數位電路 (4)---2x1MUX

以Verilog 設計一個數位電路 (4)---2x1MUX

`timescale 1 ns/1 ns

module EX_104 (a, b, c, sel);
input a, b, sel;
output c;
wire c;

assign c = ( sel == 1'b1 ) ? a : b;

endmodule

`timescale 100 ns/1 ns

module testbench;

reg a, b, sel;

wire c;

EX_104 UUT(

.a(a),

.b(b),

.c(c),

.sel(sel) );

integer i;

initial

begin

for (i=0;i<=7;i=i+1)begin

{sel,a,b}=i;

#20;

end

#20;

$stop;

end

endmodule

以Verilog 設計一個數位電路 (3)---and , not 邏輯閘

以Verilog 設計一個數位電路 (3)---and , not 邏輯閘

`timescale 1 ns/1 ns

module EX_103 (in1, in2, out1, out2);
input [3:0] in1, in2;
output [3:0] out1;
output out2;

wire [3:0]out1;
wire out2;

assign out1 = ~in1 & in2;
assign out2 = ~&in2;

endmodule

//=======================

// Test Bench

//=======================

`timescale 100ns/1 ns

module testbench;
reg [3:0]in1, in2;
wire [3:0]out1;
wire out2;
integer i;
EX_103 UUT(.in1(in1), .in2(in2), .out1(out1), .out2(out2) );
initial
begin
for (i=0;i<=3;i=i+1) begin
{in2[0],in1[0]}=i; {in2[1],in1[1]}=i;
{in2[2],in1[2]}=i; {in2[3],in1[3]}=i;

#20;

end

for (i=0;i<=15;i=i+1) begin
{in2}=i;

#20;
end
#20;
$stop;
end

以Verilog 設計一個數位電路 (2)---and , not 邏輯閘

以Verilog 設計一個數位電路 (2)---and , not 邏輯閘

自動產生的verilog 程式
module block1(
in1,
in2,
out1
);

input in1;
input in2;
output out1;

wire SYNTHESIZED_WIRE_0;
assign SYNTHESIZED_WIRE_0 = ~in1;
assign out1 = SYNTHESIZED_WIRE_0 & in2;

endmodule

程式與測試平台程式

`timescale 1 ns/1 ns

module EX_102 (in1, in2, out1);
input in1, in2;
output out1;
wire in1, in2;
wire out1;

assign out1 = ~in1 & in2;

endmodule

//=============================
//測試平台
//=============================
`timescale 100 ns/1 ns

module testbench;
reg in1, in2;
wire out1;

EX_102 UUT(
.in1(in1),
.in2(in2),
.out1(out1) );
initial
begin
in1 = 1'b0; // Time = 0
in2 = 1'b0;

#50; // Time = 50
in2 = 1'b0; in1 = 1'b1;

#50; // Time = 100
in2 = 1'b1; in1 = 1'b0;

#50; // Time = 150
in2 = 1'b1; in1 = 1'b1;

#50;
$stop;

end

endmodule

以Verilog 設計一個數位電路 (1)

自動產生的Verilog 程式
module block1(
a,
b,
c,
d,
en,
sel,
f
);

input a;
input b;
input c;
input d;
input en;
input sel;
output f;

wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;

assign SYNTHESIZED_WIRE_2 = b | a;
assign SYNTHESIZED_WIRE_3 = d | c;

assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_2 & en;
assign SYNTHESIZED_WIRE_1 = en & SYNTHESIZED_WIRE_3;

Block2 b2v_inst12(
.I0(SYNTHESIZED_WIRE_0),
.sel(sel),
.I1(SYNTHESIZED_WIRE_1),
.Y(f));

endmodule

程式與測試平台

`timescale 1 ns/1 ns

module EX_101 (a, b, c, d, en, sel, f);

input a, b, c, d, en, sel;

output f;

wire f;

wire g, h, i, j;

assign g = a | b;

assign i = g & en;

assign h = c | d;

assign j = h & en;

assign f = (sel==1'b0) ? i : j;

// f= ( (sel' (a+b)*en) + sel (c+d)*en )

endmodule

//=========Test Bench===============

`timescale 100 ns/1 ns

module testbench;

reg a, b, c, d, en, sel;

wire f;

EX_101 UUT(

.a(a),

.b(b),

.c(c),

.d(d),

.en(en),

.sel(sel),

.f(f) );

initial

begin

a = 1'b0; // Time = 0

b = 1'b1;

c = 1'b0;

d = 1'b1;

en = 1'b0; sel = 1'b0;

#10; // Time = 10

en = 1'b1; sel = 1'b0;

#10; // Time = 20

en = 1'b0; sel = 1'b1;

#10; // Time = 30

en = 1'b1; sel = 1'b1;

#10

a = 1'b1; // Time = 40

b = 1'b0;

c = 1'b1;

d = 1'b0;

en = 1'b0; sel = 1'b0;

#10; // Time = 50

en = 1'b1; sel = 1'b0;

#10; // Time = 60

en = 1'b0; sel = 1'b1;

#10; // Time = 70

en = 1'b1; sel = 1'b1;

#10; // Time = 80

$stop;

end

endmodule

The Ultimate Guide to Python: How to Go From Beginner to Pro

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2020年5月5日 星期二

2020年5月3日 星期日

The Ultimate Guide to Python: How to Go From Beginner to Pro

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2020年5月5日星期二

2020年5月3日星期日