Common-cathod seven segment display in Verilog

Common-cathod seven segment display in Verilog

//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//----------------------------------------- 
module seven_7segDisplay_CA(hex,seg);

input [3:0] hex;
output reg [7:0] seg;

// segment encoding
//      0
//     ---  
//  5 |   | 1
//     ---   <- 6
//  4 |   | 2
//     ---
//      3

always @(hex)
begin
   case (hex)
       // Dot point is always disable
       4'b0001 : seg = 8'b11111001;   //1 = F9H
       4'b0010 : seg = 8'b10100100;   //2 = A4H
       4'b0011 : seg = 8'b10110000;   //3 = B0H
       4'b0100 : seg = 8'b10011001;   //4 = 99H
       4'b0101 : seg = 8'b10010010;   //5 = 92H
       4'b0110 : seg = 8'b10000010;   //6 = 82H
       4'b0111 : seg = 8'b11111000;   //7 = F8H
       4'b1000 : seg = 8'b10000000;   //8 = 80H
       4'b1001 : seg = 8'b10010000;   //9 = 90H
       4'b1010 : seg = 8'b10001000;   //A = 88H
       4'b1011 : seg = 8'b10000011;   //b = 83H
       4'b1100 : seg = 8'b11000110;   //C = C6H
       4'b1101 : seg = 8'b10100001;   //d = A1H
       4'b1110 : seg = 8'b10000110;   //E = 86H
       4'b1111 : seg = 8'b10001110;   //F = 8EH
       default : seg = 8'b11000000;   //0 = C0H
    endcase
end

endmodule

// 時間單位 1ns, 時間精確度10 ps
`timescale 10ns/10ps 
module TB;
/*
module seven_7segDisplay_CA(hex,seg);
input [3:0] hex;
output reg [7:0] seg;
*/

// Inputs
    reg [3:0] hex;

// Outputs
    wire [7:0] seg;

// Instantiate the UUT
seven_7segDisplay_CA UUT (
        .hex(hex), 
        .seg(seg) );

// Initialize Inputs

initial $monitor($time, "seg = %h,  hex = %h", seg, hex);
// Initialize Inputs
initial begin
  hex = 4'h00;
end  

always
  #10 hex = hex + 4'h01;

 initial #160 $finish; //Complete simulation after 160 units

endmodule

4 to 1 multiplexer using case in Verilog

4 to 1 multiplexer using case in Verilog

//--------------------------------------------------
//4 to 1 multiplexer using case....endcase statement
//--------------------------------------------------
module MUX_4x1( s,i, y);

input [1:0] s;   //Selection signal
input [3:0] i;   //4-bit input
output reg y;

always @(s or i)
begin
   case (s)
      2'b00 : y = i[0];
      2'b01 : y = i[1];
      2'b10 : y = i[2];
      2'b11 : y = i[3];
      default : y = 1'b0;
   endcase
end
endmodule

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps 

module TB;

/*

module MUX_4x1( s,i, y);

input [1:0] s;   //Selection signal

input [3:0] i;   //4-bit input

output reg y;

*/

// Inputs

    reg [1:0] s;

    reg [3:0] i;

// Outputs

    wire y;

// Instantiate the UUT

 MUX_4x1 UUT( 

        .y(y), 

        .s(s), 

        .i(i)  );

// Initialize Inputs

initial

 $monitor ($time,"y=%b, s=%b, i=%b", y, s, i);

initial //Initialize input signals

 begin

    s = 2'b00;

    i = 4'b0101;

 end

initial 

 begin

   #20  s = 2'b01;   //Set selection at different times

   #20  s = 2'b10;

   #20  s = 2'b11;

 end

initial #100 $finish;  //Complete simulation after 120 time units

  

endmodule

1 to 4 Demultiplexer in Verilog

1 to 4 Demultiplexer  in Verilog

//---------------------------------------------------------
//1 to 4 Demultiplexer using nesting if...else..statement
//---------------------------------------------------------
module DeMux_1x4(I, S0, S1 ,y );

input I;
input S0, S1;     //Selection signals
output reg [3:0] y;

always @ (I or S0 or S1)
  begin
    if (S1==1'b0)
      begin
    if (S0==1'b0)
           y = {3'b000, I};    //marge 000 with I to y
        else
           y = {2'b00, I, 1'b0};
  end
    else
      begin 
    if (S0==1'b0)
           y = {1'b0, I, 2'b00};
        else
           y = {I, 3'b000};
  end
  end

endmodule

// 時間單位 1ns, 時間精確度10 ps
`timescale 10ns/10ps 
module TB;
/*
module DeMux_1x4(I, S0, S1 ,y );
input I;
input S0, S1;     //Selection signals
output reg [3:0] y;
*/

// Inputs
    reg I;
    reg S0;
    reg S1;

// Outputs
    wire [3:0] y;

// Instantiate the UUT
DeMux_1x4 UUT (
        .y(y), 
        .I(I), 
        .S0(S0), 
        .S1(S1));

initial $monitor($time, "y = %b,  I = %b,  S0 = %b,  S1 = %b", y, I, S0, S1);
// Initialize Inputs
integer i,j;

initial begin
for (i=0;i<=3;i=i+1) begin
{S1,S0}=i;

for (j=0;j<=1;j=j+1) begin
I=j;
#20;
end
end
#20 
$stop;
end  
endmodule

4x1 MUX in Verilog

4x1 MUX in Verilog

//-------------------------------------------------------

//4-bit multiplexer with if...else if...else if...else...

//-------------------------------------------------------

module MUX_4x1(s, i ,y);

input [1:0] s;   //Select line

input [3:0] i;    //Input data

output reg y;

always @ (s or i)

  begin

    if (s==2'b00)

      y = i[0];

    else if (s==2'b01)

      y = i[1];

    else if (s==2'b10)

      y = i[2];

    else

      y = i[3];

  end

endmodule

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps 

module TB;

/*

module mul4_1_if(s, i ,y);

input [1:0] s;   //Select line

input [3:0] i;    //Input data

output reg y;

*/

// Inputs

    reg [1:0] s;

    reg [3:0] i;

// Outputs

    wire y;

// Instantiate the UUT

 MUX_4x1 UUT( 

        .y(y), 

        .s(s), 

        .i(i)  );

// Initialize Inputs

initial

 $monitor ($time,"y=%b, s=%b, i=%b", y, s, i);

initial //Initialize input signals

 begin

    s = 2'b00;

    i = 4'b0101;

 end

initial 

 begin

   #20  s = 2'b01;   //Set selection at different times

   #20  s = 2'b10;

   #20  s = 2'b11;

 end

initial #100 $finish;  //Complete simulation after 120 time units

  

endmodule

4-bit Magnitude Comparator in Verilog

4-bit Magnitude Comparator   in  Verilog

//-----------------------------------------
// 4-bit Comparator  
// (if...else if...else)
//-----------------------------------------
module Comparator( a, b , eq, gt, lt);

// Port Declarations
input [3:0] a, b; //4-bit inputs
output reg eq, gt, lt;  //outputs eq:Equal, gt:Great than, lt:Less than

always @ (a or b)
 begin
   if (a==b)
    begin
     eq = 1'b1; gt = 1'b0; lt = 1'b0;
    end
  else if (a > b)
    begin
     eq = 1'b0; gt = 1'b1; lt = 1'b0;
    end
  else
    begin
     eq = 1'b0; gt = 1'b0; lt = 1'b1;
    end
 end
endmodule

4-bit 2 to 1 multiplexer in Verilog

4-bit 2 to 1 multiplexer in Verilog

//--------------------------------

//4-bit 2 to 1 multiplexer

//--------------------------------

module Mux2x1_4bit( s, a, b, y);

input s;           //Select signal

input [3:0] a, b;  //Input data

output reg [3:0] y;

always @ (s or a or b)

 if (s)

   y = b;

 else

   y = a;

endmodule

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps 

module TB;

/*

module Mux2x1_4bit( s, a, b, y);

input s;           //Select signal

input [3:0] a, b;  //Input data

output reg [3:0] y;

*/

// Inputs

    reg s;

    reg [3:0] a;

    reg [3:0] b;

// Outputs

    wire [3:0] y;

// Instantiate the UUT

Mux2x1_4bit UUT (

        .y(y), 

        .s(s), 

        .a(a), 

        .b(b)

        );

// Initialize Inputs

integer i;

initial begin

    b = 4'b1010; s=1'b0;

    for (i=0; i<16; i=i+1) begin

          a = i;

         #35;

    end

    a = 4'b0101; s=1'b1;

    for (i=0; i<16; i=i+1) begin

          b = i;

         #35;

    end

        

    

    #25

     $stop;

end

endmodule

4-bit latch in Verilog

4-bit latch  in Verilog

//------------------------------------
//4-bit latch using if... statement
//------------------------------------
module Latch_4bit(load, din , y);

input load;     //latch signal
input [3:0] din;

output reg [3:0] y;

always @ (din or load)
 begin
  if (load)
    y = din;
 end
endmodule


// 時間單位 1ns, 時間精確度10 ps
`timescale 10ns/10ps 
module TB;
/*
module Latch_4bit(load, din , y);
input load;     //latch signal
input [3:0] din;
output reg [3:0] y;
*/
// Inputs
    reg load;
    reg [3:0]din=4'b0000;

// Outputs
    wire [3:0] y;

// Instantiate the UUT
Latch_4bit UUT (load, din , y);
integer i;
initial begin
    for (i=0; i<32; i=i+1) begin
          {load,din} = i;
         #35;
    end
    #25
     $stop;
end


endmodule