VERILOG PROGRAM- Carry Look Ahead Adder

module CLA_4bit_adder(a,b,cin,sum,cout);
input[3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire p0,p1,p2,p3,g0,g1,g2,g3,c1,c2,c3,c4;
assign p0=(a[0]^b[0]),
p1=(a[1]^b[1]),
p2=(a[2]^b[2]),
p3=(a[3]^b[3]);
assign g0=(a[0]&b[0]),
g1=(a[1]&b[1]),
g2=(a[2]&b[2]),
g3=(a[3]&b[3]);
assign c0=cin,
c1=g0|(p0&cin),
c2=g1|(p1&g0)|(p1&p0&cin),
c3=g2|(p2&g1)|(p2&p1&g0)|(p1&p1&p0&cin),
c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&cin);
assign sum[0]=p0^c0,
sum[1]=p1^c1,
sum[2]=p2^c2,
sum[3]=p3^c3;
assign cout=c4;

endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps     
module test;
   
reg [3:0] t_a=4'b0000;
reg [3:0] t_b=4'b0000;
reg t_cin=1'b0;   
wire [3:0] t_sum;
wire t_cout;

integer i;
   
CLA_4bit_adder  DUT (.a(t_a),.b(t_b),.cin(t_cin),.sum(t_sum),.cout(t_cout));
   
// initial程序結構區塊, 產生A、B輸入信號波形
initial begin
    $monitor(t_a,t_b,t_cin,t_sum,t_cout);
    for (i=0; i<16; i=i+1) begin
        {t_a} = i;
        {t_b} = i;
         t_cin=1'b0;
        #20;
    end
end

initial
begin
  #360;   // 模擬終止時間  400 ns
    $stop;
end
   
endmodule