VERILOG 4bit Adder

VERILOG  4bit Adder

module multibit_adder_4(a,b,cin,sum,cout);
input [3:0] a,b;
input cin;
output [3:0]sum;
output cout;
assign {cout,sum}=a+b+cin;
endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module Test_bench;
reg [3:0]a,b = 4'b0000;   //  暫存器資料初值為‘0000’
reg cin;
wire [3:0]sum;
wire cout;

integer i;

multibit_adder_4 DUT(.a(a), .b(b), .cin(cin),.sum(sum),.cout(cout) );
// initial程序結構區塊, 產生A、B輸入信號波形
initial begin
    $monitor(a,b,cin,sum,cout);
    for (i=0; i<16; i=i+1) begin
        {a} = i;
        b=4'b0101;
        cin=1;
        #20;
    end
end

initial
begin
  #340;   // 模擬終止時間  200 ns
    $stop;
end

endmodule