NOR Gate Latch Verilog

NOR Gate Latch  Verilog

// file: sr_latch.v

// Using Verilog to describe our SR Latch

module SR_Latch(

    input wire S, R,

    output wire Q, Qn);

    assign Q   =  ~(R | Qn);

    assign Qn  =  ~(S | Q);

    

endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps

module Test_bench;

    reg  S,R;

    wire Q,Qn;

SR_Latch  DUT(

.S(S),

.R(R),

.Q(Q),

.Qn(Qn) );

    

initial begin

    

    $monitor(S,R,Q,Qn);

    // Initialize Inputs

    S = 0;

    R = 0;

     

    // Add stimulus here

    #100 S = 0; R = 1;

    #100 S = 1; R = 0;

    #100 S = 1; R = 1;

    #100 R = 1; R = 0;

    #100 S = 0; R = 0;

    #100 S = 1; R = 1;

    #100 S = 0; R = 0;

    #100 ;  $stop;

end

endmodule