SR Latch (gated) Verilog

SR Latch (gated) Verilog

module SR_Latch_gated(S,R,G,Q,Qn);
   output Q;
   output Qn;
   input  G; 
   input  S;
   input  R;

   wire   S1;
   wire   R1;
 
   and(S1, G, S);
   and(R1, G, R); 
   nor(Qn, S1, Q);
   nor(Q, R1, Qn);
 

endmodule



// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module Test_bench;
    reg  S,R,G;
    wire Q,Qn;

//SR_Latch_gated(S,R,G,Q,Qn);

SR_Latch_gated  DUT(
.S(S),
.R(R),
.G(G),
.Q(Q),
.Qn(Qn) );
   
initial begin
   
    $monitor(S,R,G,Q,Qn);
    // Initialize Inputs
    S = 0;
    R = 1;
    G = 1;
    // Add stimulus here
    #100 S = 0; R = 1;
    #100 S = 1; R = 0;
    #100 S = 1; R = 1;
    #100 R = 1; R = 0;
    #100 S = 0; R = 0;
    #100 S = 1; R = 1;
    #100 S = 0; R = 0;
   
    G = 0;
    #100 S = 0; R = 1;
    #100 S = 1; R = 0;
    #100 S = 1; R = 1;
    #100 R = 1; R = 0;
    #100 S = 0; R = 0;
    #100 S = 1; R = 1;
    #100 S = 0; R = 0; 
   
   
    #100 ;  $stop;
end

endmodule