http://techmasterplus.com/verilog/logicgates.php
Verilog program for Basic Logic Gates
Verilog program for Half Adder
Verilog program for Full Adder
Verilog program for 4bit Adder
Verilog program for Half Substractor
Verilog program for Full Substractor
Verilog program for 4bit Substractor
Verilog program for Carry Look Ahead Adder
Verilog program for 3:8 Decoder
Verilog program for 8:3 Encoder
Verilog program for 1:8 Demultiplxer
Verilog program for 8:1 Multiplexer
Verilog program for 8bit D Flipflop
Verilog program for T Flipflop
Verilog program for JK Flipflop
Verilog program for Equality Comparator
Verilog program for 8bit Up down counter
Verilog program for 8bit Shift Register (SIPO,PISO,PIPO)
Verilog program for Random Access Memory(RAM)
Verilog program for Programmable clock Generator
Verilog program for Finite State Machine (mealy)
Verilog program for Finite State Machine (moore)
1-out-of-4 脈衝位置編碼 (PPM)
1-out-of-4 脈衝位置編碼 (PPM) 1-out-of-4 脈衝位置編碼 (PPM) ，主要概念是將一個訊號週期（Symbol）等分成 4 個時段（Slots）。根據資料數值（0, 1, 2, 或 3），脈衝會出現在對應的時段中。 import tkinter as ...
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課程講義 下載 11/20 1) PPT 下載 + 程式下載 http://www.mediafire.com/file/cru4py7e8pptfda/106%E5%8B%A4%E7%9B%8A2-1.rar 11/27 2) PPT 下載...
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Line 發報機 Python TKinter (CONFIG_LINE Message API_2.py) import serial import serial.tools.list_ports import tkinter as tk from tkinter import...
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