以Verilog 設計一個數位電路 (EX1-1)--- 74LS139

以Verilog 設計一個數位電路 (EX1-1)--- 74LS139

`timescale 1 ns/1 ns

module ex1_74LS139 (A, B, G, Y);
input A,B,G;
output [3:0]Y;


assign Y[0]= ~G & (~A & ~B);
assign Y[1]= ~G & (~A &  B);
assign Y[2]= ~G & ( A & ~B);
assign Y[3]= ~G & ( A &  B);

endmodule

`timescale 100 ns/1 ns

module TB;

reg A,B,G;

wire [3:0]Y;

integer i;

ex1_74LS139 UUT (A, B, G, Y);

initial 

begin

for (i=0;i<=7;i=i+1) begin

{G,A,B}=i;

#20;

end

#20;

$stop;

end

endmodule

以Verilog 設計一個數位電路 (12)--- Shift Rotate

以Verilog 設計一個數位電路 (12)--- Shift  Rotate

`timescale 1 ns/1 ns

module EX_112 (a, b, c, d);
input [7:0] a;
output [7:0] b, c, d;
wire [7:0] b, c, d;

assign b = { a[6:0], a[7] };

assign c = { a[0], a[7:1] };

assign d = { a[3:0], a[7:4] };


endmodule

`timescale 100 ns/1 ns

module testbench;

reg [7:0] a;

wire [7:0] b, c, d;

EX_112 UUT (

.a(a),

.b(b),

.c(c),

.d(d) );

initial

begin

 a   = 8'h0f; // Time = 0

 #50; // Time = 50

 a   = 8'h5a;

 #50

  $stop;

end

endmodule

以Verilog 設計一個數位電路 (11)--- unsigned , signed + *

以Verilog 設計一個數位電路 (11)--- unsigned , signed + * 

Hex value:
35 × 76 = 186E
Hex value:
186E + 9a = 1908

`timescale 1 ns/1 ns

module EX_111 (a, b, c, k_usgn, k_sgn);
input [7:0] a, b, c;
output [15:0] k_usgn, k_sgn;
wire [15:0] k_usgn, k_sgn;

wire [7:0] d_usgn, e_usgn, d_sgn, e_sgn;
wire [15:0] tmp_usgn, tmp_sgn;

// for unsigned operation
assign tmp_usgn = a * b;

assign {d_usgn, e_usgn} = tmp_usgn + {8'h00,c};

assign k_usgn = {d_usgn, e_usgn};


// for signed operation
assign tmp_sgn = {{8{a[7]}},a} * {{8{b[7]}},b};

assign {d_sgn , e_sgn } = tmp_sgn  + {{8{c[7]}},c};

assign k_sgn = {d_sgn, e_sgn};


endmodule

//================================

`timescale 100 ns/1 ns

module testbench;

reg [7:0] a, b, c;

wire[15:0] k_usgn, k_sgn;

EX_111 UUT(

.a(a),

.b(b),

.c(c),

.k_usgn(k_usgn),

.k_sgn(k_sgn) );

initial

begin

 a   = 8'h35; // Time = 0

 b   = 8'h76;

 c   = 8'h9a;

 #50; // Time = 50

 a   = 8'h18;

 b   = 8'h86;

 c   = 8'h51;

 #50;

 $stop;

end

endmodule

以Verilog 設計一個數位電路 (10)--- arithmetic + - x /

以Verilog 設計一個數位電路 (10)--- arithmetic + - x / 

Hex value:
55 × 86 = 2C7E

Hex value:
289A × 4 = A268

Hex value:
2C7E + A268 = CEE6



`timescale 1 ns/1 ns

module EX_110 (a, b, c, d);
input [7:0] a, b;
input [15:0] c;
output [15:0] d;
wire [15:0] d;

wire [15:0] tmp;

assign tmp = a * b;

assign d = tmp + (c<<2);


endmodule

`timescale 100ns/1 ns

module testbench;
reg [7:0] a, b;
reg [15:0] c;
wire [15:0] d;

EX_110 UUT(
.a(a),
.b(b),
.c(c),
.d(d) );
initial
begin
 a   = 8'h55; // Time = 0
 b   = 8'h86;
 c   = 16'h289a;

 #50; // Time = 50
 a   = 8'h54;
 b   = 8'h96;
 c   = 16'h067a;

 #50;
 $stop;
end

endmodule

以Verilog 設計一個數位電路 (9)---Parallel 4x1 MUX

以Verilog 設計一個數位電路 (9)---Parallel 4x1 MUX

`timescale 1 ns/1 ns

module EX_109 (a, b, c, d, sel, e);
input [7:0] a, b, c, d;
input [1:0] sel;
output [7:0] e;
wire [7:0] e;

assign e = (sel==2'b00) ? a :
            (sel==2'b01) ? b :
            (sel==2'b10) ? c : d;

endmodule

`timescale 100 ns/1 ns

module testbench;

reg [7:0] a, b, c, d;

reg [1:0] sel;

wire [7:0] e;

EX_109 UUT (

.a(a),

.b(b),

.c(c),

.d(d),

.sel(sel),

.e(e) );

initial

begin

 a   = 8'h00; // Time = 0

 b   = 8'h55;

 c   = 8'haa;

 d   = 8'hff;

 sel = 2'b00;

 #20; // Time = 20

 sel = 2'b01;

 #20; // Time = 40

 sel = 2'b10;

 #20; // Time = 60

 sel = 3'b11;

 #20;

 $stop;

 

end

endmodule

以Verilog 設計一個數位電路 (8)---True table

以Verilog 設計一個數位電路 (8)---True table

`timescale 1 ns/1 ns

module EX_108 (a, f);
input [2:0] a;
output [3:0] f;
wire [3:0] f;

assign f[3] = (~a[2] & ~a[1] & ~a[0]) |
       (~a[2] & ~a[1] &  a[0]) |
       ( a[2] &  a[1] &  a[0]);

assign f[2] = (~a[2] &  a[1] & ~a[0]) |
       ( a[2] & ~a[1] & ~a[0]) |
       ( a[2] &  a[1] &  a[0]);

assign f[1] = (~a[2] & ~a[1] &  a[0]) |
       (~a[2] &  a[1] & ~a[0]) |
       ( a[2] &  a[1] &  a[0]);

assign f[0] = (~a[2] & ~a[1] & ~a[0]) |
       ( a[2] & ~a[1] &  a[0]);

endmodule

/*
true_table
 a   f
000 1001
001 1010
010 0110
011 0000
100 0100
101 0001
110 0000
111 1110
*/

`timescale 100ns/1 ns

module testbench;
reg [2:0] a;
wire [3:0] f;

EX_108 UUT(
.a(a),
.f(f) );
initial
begin
 a    = 3'b000; // Time = 0
 #20; // Time = 20
 a    = 3'b001;
 #20; // Time = 40
 a    = 3'b010;
 #20; // Time = 60
 a    = 3'b011;
 #20; // Time = 80
 a    = 3'b100;
 #20; // Time = 100
 a    = 3'b101;
 #20; // Time = 120
 a    = 3'b110;
 #20; // Time = 140
 a    = 3'b111;
end
endmodule

以Verilog 設計一個數位電路 (7)---True table

以Verilog 設計一個數位電路 (7) ---True table 

`timescale 1 ns/1 ns

module EX_107 (a, f);
input [2:0] a;
output [3:0] f;
wire [3:0] f;

assign f = ( a==3'b000 ) ? 4'b1001 :
            ( a==3'b001 ) ? 4'b1010 :
            ( a==3'b010 ) ? 4'b0110 :
            ( a==3'b011 ) ? 4'b0000 :
            ( a==3'b100 ) ? 4'b0100 :
            ( a==3'b101 ) ? 4'b0001 :
            ( a==3'b110 ) ? 4'b0000 : 4'b1110 ;

endmodule

/*
true_table
 a   f
000 1001
001 1010
010 0110
011 0000
100 0100
101 0001
110 0000
111 1110
*/

`timescale 100 ns/1 ns

module testbench;
reg [2:0] a;
wire [3:0] f;

EX_107 UUT(
.a(a),
.f(f) );
initial
begin
 a    = 3'b000; // Time = 0
 #20; // Time = 20
 a    = 3'b001;
 #20; // Time = 40
 a    = 3'b010;
 #20; // Time = 60
 a    = 3'b011;
 #20; // Time = 80
 a    = 3'b100;
 #20; // Time = 100
 a    = 3'b101;
 #20; // Time = 120
 a    = 3'b110;
 #20; // Time = 140
 a    = 3'b111;
end
endmodule